Search - WISHBONE

Search - WISHBONE - List

【VHDL-FPGA-Verilog】 sdcard.tar DL : 0: 最新的基于wishbone总线的sd卡控制器设计-Latest sd card controller design based on the wishbone bus
Update : 2024-05-09 Size : 2286592 Publisher : shijianshu
【Compress-Decompress algrithms】 ahb2wishbone_latest.tar DL : 1: AHB to Wishbone memory interface VHDL source code
Update : 2024-05-09 Size : 10638336 Publisher : cyf
【VHDL-FPGA-Verilog】 RD1088_rev01.2 DL : 0: FPGA或CPLD读取SD卡的IP核，基于wishbone接口，支持SDHC2.0，包含了使用说明，为Verilog语言编写-FPGA or CPLD reads the SD card IP core, based on the wishbone interface, support SDHC2.0, contains instructions for the Verilog language
Update : 2024-05-09 Size : 1403904 Publisher : andy
【Other】 Ethernet_MAC_10-100-Mbps_latest.tar DL : 0: The Ethernet IP Core is a MAC (Media Access Controller). It connects to the Ethernet PHY chip on one side and to the WISHBONE SoC bus on the other. The core has been designed to offer as much flexibility as possible to all kinds of applications.-The Ethernet IP Core is a MAC (Media Access Controller). It connects to the Ethernet PHY chip on one side and to the WISHBONE SoC bus on the other. The core has been designed to offer as much flexibility as possible to all kinds of applications.
Update : 2024-05-09 Size : 19430400 Publisher : ke
【VHDL-FPGA-Verilog】 ethernet_10ge_mac_latest.tar DL : 0: The 10GE MAC core is designed for easy integration with proprietary custom logic. It features a POS-L3 like interface for the datapath and a Wishbone compliant interface for management. The core was intentionally designed with a limited feature set for a small gate footprint.
Update : 2024-05-09 Size : 926720 Publisher : ke
【VHDL-FPGA-Verilog】 IDE_VHDL DL : 0: 此代码为wishbone公司的IDE协议主机端VHDL源代码，有三个版本，实现了UDMA。版权归wishbone公司，请勿用于商业用途。-This VHDL codes with threr versions implemented IDE host protocol，supporting with UDMA。
Update : 2024-05-09 Size : 549888 Publisher : CHEN KANG
【VHDL-FPGA-Verilog】 the-PCIE-interface-design DL : 0: 基于wishbone和端点IP的PCIE接口设计，介绍了PCIE硬核端点模块和wishbone总线规范，应用WHDL语言，编程实现了wishbone总线的主从端口-Based the PCIE interface design of the wishbone and the endpoint IP, PCIE hard core endpoint module and Wishbone bus specification, application WHDL language programming the wishbone bus master and slave port
Update : 2024-05-09 Size : 299008 Publisher : 张轶
【VHDL-FPGA-Verilog】 uart DL : 0: 基于wishbone的 uart 通信设计-The uart communication design based wishbone
Update : 2024-05-09 Size : 24576 Publisher : 赵奥飞
【VHDL-FPGA-Verilog】 rng DL : 0: wishbone规格下的rng代码的实现，自己编写顶层模块可以在modelsim下实现仿真-wishbone rng specifications under the implementation of the code, you can write your own top-level module under modelsim for simulation
Update : 2024-05-09 Size : 2048 Publisher : 孙晓明
【VHDL-FPGA-Verilog】 WISHBONE_conmax DL : 0: 很详细的wishbone总线学习借鉴代码和文档-Very detailed wishbone bus to learn from the code and documentation
Update : 2024-05-09 Size : 666624 Publisher : haizi
【ARM-PowerPC-ColdFire-MIPS】 minsoc DL : 0: 片上处理器加上外设的设计,基于openrisc指令集，wishbone总线协议的一款基于FPGA的片上处理器-processor of on-chip
Update : 2024-05-09 Size : 10304512 Publisher : 云海
【VHDL-FPGA-Verilog】 wb_dma_latest.tar DL : 0: 这是一个简单IP核的DMA桥，他有两个WISHBONE接口，该平台可实现在两个相同或不同接口之间DMA数据的搬运。-This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces.
Update : 2024-05-09 Size : 143360 Publisher : 云海
【VHDL-FPGA-Verilog】 i2c_latest.tar DL : 0: i2C总线的控制器核，实现了I2C的主站功能。-I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Master Core provides an interface between a Wishbone Master and an I2C bus. It is an easy path to add I2C capabilities to any Wishbone compatible system. You can find the I2C specifications on Phillips web Site. Work was originally started by Frédéric Renet.
Update : 2024-05-09 Size : 1479680 Publisher :
【ARM-PowerPC-ColdFire-MIPS】 jtag_memory_v0.12 DL : 0: JTAG调试接口与testbench，附加memory模块并支持cpu和wishbone-JTAG TAP with Controller and testbench ,and an addition of block memory and the potential support of cpu and wishbone
Update : 2024-05-09 Size : 13090816 Publisher : 石丰略
【VHDL-FPGA-Verilog】 i2s_latest DL : 0: Details Name: i2s Created: Mar 22, 2004 Updated: Jan 10, 2014 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other project properties Category: Communication controller Language: VHDL Development status: Additional info: Design done WishBone Compliant: No License:
Update : 2024-05-09 Size : 5120 Publisher : chen
【VHDL-FPGA-Verilog】 verilog_cordic_core DL : 0: A highly configurable 1st quadrant CORDIC core in verilog-Details Name: verilog_cordic_core Created: Sep 14, 2008 Updated: Aug 12, 2011 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other project properties Category: Arithmetic core Language: Verilog Development status: Additional info: Design done, FPGA proven WishBone Compliant: No License: Description
Update : 2024-05-09 Size : 359424 Publisher : chen
【ARM-PowerPC-ColdFire-MIPS】 I2C DL : 0: 一个基于wishbone总线的I2C控制器以及测试文件-wishbone I2C
Update : 2024-05-09 Size : 231424 Publisher : 范献军
【VHDL-FPGA-Verilog】 i2c DL : 0: wishbone to avalon 介面 I2C-wishbone to avalon I2C interface
Update : 2024-05-09 Size : 173056 Publisher : chang
【VHDL-FPGA-Verilog】 verilog-arbiter.tar DL : 0: Verilog arbitrator for Wishbone R3 compliant bus
Update : 2024-05-09 Size : 5120 Publisher : corgano
【VHDL-FPGA-Verilog】 wb_sdram_ctrl.tar DL : 0: Generic Wishbone R3 compliant SDRAM controller written in Verilog
Update : 2024-05-09 Size : 10240 Publisher : corgano

« 1 2 3 4 5 6 7 89 »