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【Develop Tools】 wbspec_b3 DL : 0: soc中ip核集成时所采用的一种片上总线，开发的，为opencores所采用，wishbone片上总线指南-were integrated ip nuclear adopted by an on-chip bus, development, for opencores using the on-chip bus wishbone Guide
Update : 2008-10-13 Size : 786154 Publisher : 钱丰勇
【Other resource】 wb_conbus.tar DL : 0: wishbone 源代码，opencore-wishbone source code, opencore
Update : 2008-10-13 Size : 14905 Publisher : 姚卫忠
【Other resource】 wishbone_i2c_master DL : 0: -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr -- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues--- WISHBONE revB2 compiant I2C master core -- -- author : Richard Herveille -- rev. 0.1 based on simple_i 2c -- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman) -- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt -
Update : 2008-10-13 Size : 5470 Publisher : 郑开科
【VHDL-FPGA-Verilog】 spilicheng DL : 0: spi接口的wishbone总线的实现，能够实现spi控制器的基本功能，书上例程-spi interface wishbone bus, to achieve the basic functions of the spi controller to book routine
Update : 2024-05-08 Size : 2250752 Publisher : 在
【VHDL-FPGA-Verilog】 wishbone DL : 0: wishbone接口的设计，在交换机和MAC之间建立wishbone接口-the wishbone interface design, wishbone interface between the switch and MAC
Update : 2024-05-08 Size : 13312 Publisher : 周勇勃
【Software Engineering】 wishbone-slave-and-master-to-avalon-bus DL : 0: wishbone slave and master to avalon bus verilog
Update : 2024-05-08 Size : 1024 Publisher : lamqsb
【Other】 wishbone DL : 0: wishbone片上总线系统设计，实现基本的共享总线实例。并用modelsim进行仿真。-wishbone chip bus system design, to achieve the basic shared bus instance. And use modelsim simulation.
Update : 2024-05-08 Size : 282624 Publisher : df
【VHDL-FPGA-Verilog】 WISHBONE-Interconnect-Matrix-IP-CORE DL : 0: 来自opencores.org 开源IP 很好的资料，供大家学习-WISHBONE Interconnect Matrix IP CORE
Update : 2024-05-08 Size : 106496 Publisher : 程硕
【VHDL-FPGA-Verilog】 Wishbone DL : 0: wishbone总线的一些研究，包括一些代码-wishbone verilog
Update : 2024-05-08 Size : 271360 Publisher : 浩慧
【VHDL-FPGA-Verilog】 wishbone-flash- DL : 0: wishbone总线的Flash闪存接口设计的相关资料-relevant information wishbone bus Flash memory interface design
Update : 2024-05-08 Size : 286720 Publisher : 浩慧
【VHDL-FPGA-Verilog】 wishbone DL : 0: Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期数据总线宽度可以是8-64位支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联握手协议，允许速率控制可以达到每个时钟周期进行一次数据传输支持普通周期结束、重试结束、错误结束等总线周期形式支持用户自定义的标志:采用MASTER/SLAVE体系结构支持多点进程(Multi-MASTER):仲裁算法用于定义支持各种各样的IP核互联，包括USB、双向总线、复用器互联等同步逻辑设计非常简单的时序标准与硬件实现技术无关(FPGA, ASIC等) 与设计工具无关。相对于其他的IP核接口规范来说，Wishbone接口规范具有简单、开放、高效、利于实现等特点而且完全免费，并没有专利保护。基于上述优点，因此采用Wishbone总线进行接口设计。本文对Wishbone总线接口的设计参考了OpenCore上的有关设计。- Wishbone specification has the following characteristics : a simple , compact, and requires very little logic gates complete common data bus data transfer protocols, including single reader , fast transmission, read-modify- write cycle, the event cycle data bus width can be 8-64 bit support big-endian (big-endian) and the small end (litle-endian), the interface automatically convert between the two. Support memory mapping , FIFO memory , cross interconnection handshake protocol that allows rate control every clock cycle to achieve a data transfer support normal cycle ends , retry the end , wrong end of the bus cycle and other forms support for user-defined flags : The MASTER/SLAVE architecture supports multi- process (Multi-MASTER): arbitration algorithm is used to define support a variety of IP cores interconnected , including USB, bi-directional bus , multiplexer interconnection , etc. synchronous logic design very simple timing standards technology-indepe
Update : 2024-05-08 Size : 12288 Publisher : 程浩武
【Linux-Unix】 wishbone-serial DL : 0: USB Wishbone-Serial adapter driver for Linux v2.13.6.
Update : 2024-05-08 Size : 1024 Publisher : fangxizing
【Linux-Unix】 wishbone-serial DL : 0: USB Wishbone-Serial adapter driver.
Update : 2024-05-08 Size : 1024 Publisher : gangdaokl
【Other】 wishbone DL : 0: gives back a datavector containing locations and angles of a double wishbone suspension
Update : 2024-05-08 Size : 2048 Publisher : anfeenee
【VHDL-FPGA-Verilog】 i2c_wishbone.tar DL : 0: verilog i2c master wishbone slave wrapper
Update : 2024-05-08 Size : 4096 Publisher : ascensor
【VHDL-FPGA-Verilog】 wb_handler-1.0.1.tar DL : 0: wishbone ctrl for fgpa - wb handler
Update : 2024-05-08 Size : 10240 Publisher : tekker
【VHDL-FPGA-Verilog】 wb_counter-1.0.1.tar DL : 0: wishbone counter for fpga
Update : 2024-05-08 Size : 11264 Publisher : tekker
【VHDL-FPGA-Verilog】 miniuart-1.0.0.tar DL : 0: wishbone uart controller
Update : 2024-05-08 Size : 104448 Publisher : tekker
【VHDL-FPGA-Verilog】 natebege-0.2.0.tar DL : 0: wishbone vhdl config tool
Update : 2024-05-08 Size : 14336 Publisher : tekker
【Other】 double wishbone tests DL : 0: double wishbone tests
Update : 2019-09-14 Size : 718594 Publisher : nrmoaz

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