Search - WISHBONE

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【Software Engineering】 wbspec_b3 DL : 0: Introduce the wishbone bus .
Update : 2024-05-08 Size : 785408 Publisher : liang
【VHDL-FPGA-Verilog】 SoCWishboneSystem DL : 0: SoC-Wishbone System IP核的VHDL语言源代码-SoC-Wishbone System IP core language VHDL source code
Update : 2024-05-08 Size : 90112 Publisher : 肖冠兰
【Software Engineering】 Wishboneandusb DL : 0: Wishbone 和 USB总线结构的介绍-Wishbone and the introduction of USB bus architecture
Update : 2024-05-08 Size : 167936 Publisher : 易学
【VHDL-FPGA-Verilog】 wishbone_i2c_master_vhd DL : 0: wishbone i2c master vhdl code
Update : 2024-05-08 Size : 5120 Publisher : 磊
【Embeded-SCM Develop】 spi_wishbone DL : 0: spi wishbone bus code
Update : 2024-05-08 Size : 49152 Publisher : 磊
【VHDL-FPGA-Verilog】 wishbone_VHDL DL : 0: wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快成为ip通信的主流-Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
Update : 2024-05-08 Size : 464896 Publisher : 王鹏
【Com Port】 uart DL : 0: uart协议、实现、验证，基于wishbone协议，工业标准为16550A-UART protocol, implementation, verification, based on the Wishbone protocol, the industry standard for the 16550A
Update : 2024-05-08 Size : 257024 Publisher : dannel218
【VHDL-FPGA-Verilog】 ethernet.tar DL : 0: VHDL MAC wishbone VHDL MAC wishbone-VHDL MACVHDL MAC wishbone VHDL MAC wishbone
Update : 2024-05-08 Size : 936960 Publisher : w7612
【Embeded-SCM Develop】 ahb2wishbone_latest.tar DL : 0: opencore ahb to wishbone bus verilog code
Update : 2024-05-08 Size : 2662400 Publisher : xiantongma
【Communication-Mobile】 wb_lpc_latest.tar DL : 0: Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.
Update : 2024-05-08 Size : 410624 Publisher : Arun
【ActiveX/DCOM/ATL】 pit_latest.tar DL : 0: Programmable Interval Timer: Overview Category :: Other Language :: Verilog Development status :: Beta WishBone Compliant :: Yes Phazes :: Design done, Specification done
Update : 2024-05-08 Size : 595968 Publisher : Arun
【VHDL-FPGA-Verilog】 ima_adpcm_encoder_latest.tar DL : 0: This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.
Update : 2024-05-08 Size : 23552 Publisher : Arun
【Video Capture】 camera_up DL : 0: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Update : 2024-05-08 Size : 32768 Publisher : 孙喆
【VHDL-FPGA-Verilog】 SDCard_Controller DL : 0: SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 -SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
Update : 2024-05-08 Size : 24576 Publisher : xiafei
【Embeded-SCM Develop】 pci.tar DL : 0: verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
Update : 2024-05-08 Size : 13253632 Publisher : yemao
【Other】 spi_master DL : 0: SPI wishbone master and verification environment
Update : 2024-05-08 Size : 2506752 Publisher : 王小墨
【Documents】 wishbone_bus_protocol DL : 0: 是一份介绍wishbone总线非常好的资料，讲的很详细，希望对大家有帮助！-This is a very good introductory information about wishbone bus , speak in great detail, I hope it is a help to all of you!
Update : 2024-05-08 Size : 1343488 Publisher : 冯谋朝
【Graph program】 wb_dma DL : 0: wishbone接口dma控制器，适合于构建soc系统，特别适用于视频开发-dma controller with wishbone interface，fitting for soc design，especially for video development.
Update : 2024-05-08 Size : 143360 Publisher : 刘月
【VHDL-FPGA-Verilog】 i2c DL : 0: 基于wishbone总线的I2C的ip核，可供学习和参考．-I2C Bus-based wishbone of ip core, available for study and reference.
Update : 2024-05-08 Size : 230400 Publisher : zhangfukang
【Internet-Network】 ethmac_latest[1].tar DL : 0: 10M/100M 以太网mac，wishbone接口，可以直接使用-10M/100M Ethernet mac, wishbone interface, you can directly use
Update : 2024-05-08 Size : 18535424 Publisher : 阳光

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