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【matlab】 wishbonecode DL : 0: Optimization of a Double Wishbone Suspension System
Update : 2024-05-09 Size : 8192 Publisher : samor
【Software Engineering】 wbspec_b3 DL : 0: opensource 社区引入的IP 互连总线，wishbone总线，这个是whitepaper. -opensource community into the IP interconnect bus, wishbone bus, this is a whitepaper.
Update : 2024-05-09 Size : 786432 Publisher : li
【VHDL-FPGA-Verilog】 open_cores_VGAcore DL : 0: 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core grasp of bus protocol
Update : 2024-05-09 Size : 2145280 Publisher : 张昕
【VHDL-FPGA-Verilog】 vga_lcd_latest.tar DL : 0: vga lcd 控制器 24位VGA控制，支持12位DVI协议-This embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost all available LCD and CRT displays The core supports a number of color modes, including 32bpp, 24bpp, 16bpp, 8bpp gray-scale, and 8bpp-pseudo color. The video memory is located outside the primary core, thus providing the most flexible memory solution. It can be located on-chip or off-chip, shared with the system’s main memory (VGA on demand) or be dedicated to the VGA system. The color lookup table is, as of core version 2.0, incorporated into the color-processor block. Pixel data is fetched automatically via the Wishbone revB.3 Master interface, making this an ideal “program-and-forget” video solution. More demanding video applications like streaming video or video games can benefit from the video-bank-switching function, which reduces flicker and cluttered imag
Update : 2024-05-09 Size : 1788928 Publisher : 安隹亚
【VHDL-FPGA-Verilog】 verilog DL : 0: PCI/WISHBONE bridge Reference Design-PCI/WISHBONE bridge Reference Design
Update : 2024-05-09 Size : 47104 Publisher :
【VHDL-FPGA-Verilog】 i2c_master_slave_core_latest.tar DL : 0: This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave. VMM Test-bench is also available.
Update : 2024-05-09 Size : 4562944 Publisher : Andrey
【VHDL-FPGA-Verilog】 a_vhd_16550_uart_latest.tar DL : 0: A UART that is compatible with the industry standard 16550D Includes wrappers for the Wishbone and AMBA APB busses
Update : 2024-05-09 Size : 119808 Publisher : Andrey
【VHDL-FPGA-Verilog】 cfi_ctrl_latest.tar DL : 0: 很好的 wishbone转CFI FLASH接口的源码，在INTERL的FLASH上已经调试通过-CFI FLASH CORE
Update : 2024-05-09 Size : 41984 Publisher : sunhuaiyi
【VHDL-FPGA-Verilog】 wb_conbus_latest.tar DL : 0: 源代码关于Verilog语言的wishbone总线-VHDL，verilog is very good
Update : 2024-05-09 Size : 27648 Publisher : 赵谦
【Embeded Linux】 wishbone_vip DL : 0: wishbone protocol verification tool
Update : 2024-05-09 Size : 1009664 Publisher : atlas
【VHDL-FPGA-Verilog】 WishboneSpecification DL : 0: WISHBONE Bus specification
Update : 2024-05-09 Size : 791552 Publisher : Yoon Lee
【VHDL-FPGA-Verilog】 wb_tdm_tb DL : 0: test bench that qualifies an avalon slave to wishbone interface right through to the end component
Update : 2024-05-09 Size : 1024 Publisher : mixdown
【MPI】 sdcard_mass_storage_controller.tar DL : 0: latest sdcard_mass_storage_controller core from opencores.org wishbone bus
Update : 2024-05-09 Size : 2286592 Publisher : asdtgg
【VHDL-FPGA-Verilog】 SPI DL : 0: Verilog编写的SPI程序，含英文原文档说明，很全的-The OpenCores simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. Enhancements to the original interface include a wider supported operating frequency range, 4 entries deep read and write FIFOs, and programmable transfer count dependent interrupt generation. The high compatibility with the M68HC11 SPI port ensures that existing software can use this core without major modifications. New software can use existing examples as a starting point. The core features an 8 bit wishbone interface.
Update : 2024-05-09 Size : 49152 Publisher : 邓楠
【VHDL-FPGA-Verilog】 pci_to_wb_latest[1].tar DL : 0: 该ip核实现了容量为16MB的、双字、可寻址存储镜像与wishbone总线的连接-This core implements a 16 MB DWord-addressable memory image in the Wishbone bus (so WB width is 32 bit). Its functionality is reduced to the minimum which is required by the PCI specification (and I m really trying to stick exactly to the specs).
Update : 2024-05-09 Size : 7168 Publisher : hxr
【VHDL-FPGA-Verilog】 wb_to_amba_latest[1].tar DL : 0: ahb总线到wishbone总线的桥接器，包括一个testbench,该版本暂不支持burst操作-A AHB master to WishBone slave bridge along with a basic testbench is included. Burst in not yet supported
Update : 2024-05-09 Size : 11264 Publisher : hxr
【VHDL-FPGA-Verilog】 simple_spi_latest.tar DL : 0: - 与摩托罗拉的SPI规格兼容 - 增强摩托罗拉MC68HC11串行外设接口 - 4项深读FIFO - 4项深写入FIFO - 中断后1代，2，3或4个转移字节 - 8位WISHBONE RevB.3经典界面 - 经营的输入时钟频率范围广泛 - 静态同步设计 - 完全可合成 - 130LUTs在Spartan-II，230在ACEX LCELLs的-- Compatible with Motorola s SPI specifications - Enhanced Motorola MC68HC11 Serial Peripheral Interface - 4 entries deep read FIFO - 4 entries deep write FIFO - Interrupt generation after 1, 2, 3, or 4 transfered bytes - 8 bit WISHBONE RevB.3 Classic interface - Operates from a wide range of input clock frequencies - Static synchronous design - Fully synthesizable - 130LUTs in a Spartan-II, 230 LCELLs in an ACEX
Update : 2024-05-09 Size : 575488 Publisher : 张居林
【Other】 i2c DL : 0: WISHBONE revB.2 compliant I2C Master controller Top-leve
Update : 2024-05-09 Size : 8192 Publisher : huang
【VHDL-FPGA-Verilog】 or1200_sopc DL : 0: 用verilog语言编写的or1200+wishbone总线+串口uart+片上ram，最小系统soc。包括片上ram的软件系统（C语言编写）都有。但下载者要使用此系统需要很多工具链，搞soc的应该都装好了。绝对原创！用quartusII11.0在Altera DE2-115上验证通过，Modelsim SE 6.5f仿真通过。-It s very strange for Chinese people communicating with each other in English. Right?
Update : 2024-05-09 Size : 31982592 Publisher : 咖啡猫
【VHDL-FPGA-Verilog】 viterb_encoder_and_decoder_latest.tar DL : 0: Category: Arithmetic core Language: Verilog Development status: Mature Additional info: Design done, Specification done WishBone Compliant: No
Update : 2024-05-09 Size : 458752 Publisher : gollasantu

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