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【Other resource】 adma DL : 0: Wishbone dma ip core
Update : 2008-10-13 Size : 7081 Publisher : liwen
【Com Port】 simple_spi DL : 0: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Update : 2008-10-13 Size : 473099 Publisher : Jack
【Other resource】 PCI_Bridge_Guest_UART DL : 1: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序，用verilog实现，ise7.1，不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~
Update : 2008-10-13 Size : 8428033 Publisher : heartbeat
【ELanguage】 rs232_syscon_v DL : 0: This a state-machine driven rs232 serial port interface to a \"Wishbone\" // type of bus.-This a state-driven machine rs232 seria l port interface to a "Wishbone" / / type of bus.
Update : 2008-10-13 Size : 11072 Publisher : weixing
【Com Port】 wishbone_i2c_master_vhd DL : 0: WISHBONE revB2 compiant I2C master core
Update : 2008-10-13 Size : 5807 Publisher : weixing
【Other resource】 opencores_i2c_master DL : 0: i2c VHDL,能够实现I2C 用的是wishbone总线
Update : 2008-10-13 Size : 193731 Publisher : wang
【Software Engineering】 Wishbone_from_opencores DL : 0: 这个是在ＯＰＥＮＣＯＲＥ上收集的wishbone总线的开发说明和指导，随着电子设计开源ＩＰ的大量应用，wishbone总线也越来越普及。
Update : 2008-10-13 Size : 837071 Publisher : 刘庆强
【Other resource】 OptimizationofaDoubleWishboneSuspensionSystem DL : 0: This demo shows how to use MATLAB, Optimization Toolbox, and Genetic Algorithm and Direct Search Toolbox to optimize the design of a double wishbone suspension system.
Update : 2008-10-13 Size : 2056712 Publisher : 阳关
【Other resource】 SoC_WishboneSystem DL : 0: SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
Update : 2008-10-13 Size : 91164 Publisher : 周华茂
【Other resource】 opb_wb DL : 0: 这是一个连通OPB和Wishbone Bus的Bridge, 能够让OPB与开源的Wishbone Bus连接通信，从而使用基于Wishbone的许多开源IP Core
Update : 2008-10-13 Size : 23535 Publisher : 古月
【Embeded-SCM Develop】 The_Analyse_And_Research_of_embeded_SoC_Bus DL : 0: 本文主要介绍和分析了在集成芯片设计中几种常用的片上系统总线－CoreConnect 总线、MBA 总线、Wishbone 总线和OCP 总线，通过比较这些总线的特性及适用范围，展望了它们的发展前景。
Update : 2008-10-13 Size : 171621 Publisher : wsj
【Other resource】 wisbone_2_ahb.tar DL : 0: ---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Description ---- ---- Implementation of Wishbone_BFM IP core according to ---- ---- Wishbone_BFM IP core specification document.
Update : 2008-10-13 Size : 2786095 Publisher : liang
【Other resource】 wb_rtc DL : 0: // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
Update : 2008-10-13 Size : 8076 Publisher : 姓名
【Software Engineering】 wbspec_b3 DL : 0: Introduce the wishbone bus .
Update : 2008-10-13 Size : 786159 Publisher : liang
【Other】 1256894 DL : 0: STW石器快速抢双叉脚本，要在巴克那记录，大家可以来-STW stone quick grab double wishbone script, it records in Barker, we can come to
Update : 2024-05-09 Size : 6144 Publisher : 大师傅上
【VHDL-FPGA-Verilog】 ethernet_vhdl DL : 0: 千兆以太网控制器.可以调整FIFO,和传输速率,在码流层进行控制.-Gigabit Ethernet controller. Can adjust FIFO, and the transmission rate, in the code stream control layer.
Update : 2024-05-09 Size : 30720 Publisher : 王晶
【VHDL-FPGA-Verilog】 eth_ocm_80_2 DL : 0: ethernet wishbone interface
Update : 2024-05-09 Size : 208896 Publisher : esl
【VHDL-FPGA-Verilog】 simple_spi.tar DL : 0: Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface. Very simple, very small.
Update : 2024-05-09 Size : 574464 Publisher : eldis
【USB develop】 usb DL : 0: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Update : 2024-05-09 Size : 6144 Publisher : polito
【matlab】 suanhenbi02 DL : 0: 汽车悬架运动学仿真/双横臂悬架/可以自由下载-Kinematics Simulation of automotive suspension/double wishbone suspension/free download
Update : 2024-05-09 Size : 1024 Publisher : fengtongming

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