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【Other】 wb-ddr DL : 0: 基于Wishbone总线的DDR控制器. -A wraper of DDR controller for wishbone bus.
Update : 2024-05-09 Size : 53248 Publisher : bob
【Com Port】 uart16550 DL : 0: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Update : 2024-05-09 Size : 1760256 Publisher : CloudZhang
【Embeded-SCM Develop】 This_is_pci-wishbone_nuclear_and_16450_serial_port DL : 0: 这是用pci-wishbone核和16450串口核在xilinx的FPGA上实现的。-This is pci-wishbone nuclear and 16450 serial port on the nucleus in xilinx FPGA-implemented.
Update : 2024-05-09 Size : 8428544 Publisher : iceskull
【Other】 ata_latest.tar DL : 0: The OCIDEC (OpenCores IDE Controller) is a WISHBONE rev.B2 compliant ATA/ATAPI-5 host implementation. The ATA (AT Attachment) interface, also known as IDE (Integrated Drive Electronics) interface, provides a simple interface to low cost non-volatile memories like hard-disk drives, DVD players, CDROM players/writers, CompactFlash and PC-Card devices.
Update : 2024-05-09 Size : 928768 Publisher : Gopi
【VHDL-FPGA-Verilog】 wishbone_m4_s8 DL : 0: wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
Update : 2024-05-09 Size : 3072 Publisher : mis_hey
【VHDL-FPGA-Verilog】 vga_lcd_latest.tar DL : 0: 此VGA/LCD控制器是revB.3版本的基于WISHBONE总线，适用于驱动CRT和LCD显示屏的嵌入式VGA驱动。-VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth.
Update : 2024-05-09 Size : 1796096 Publisher : liang
【VHDL-FPGA-Verilog】 UART_IP_core_for_wishbone DL : 0: 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
Update : 2024-05-09 Size : 39936 Publisher : 张阳
【VHDL-FPGA-Verilog】 ahb2wishbone_latest.tar DL : 0: AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code
Update : 2024-05-09 Size : 10640384 Publisher : rex
【VHDL-FPGA-Verilog】 wb_to_amba_latest.tar DL : 0: wishbone总线到AMBA总线的转换，做总线的朋友可以-wishbone bus to the AMBA bus conversion, so friends can see the bus
Update : 2024-05-09 Size : 11264 Publisher : 磊
【VHDL-FPGA-Verilog】 wb_conmax_latest.tar DL : 0: WISHBONE总线的接口实现，采用Verilog完成。能同时连接8个主设备和16个从设备。-WISHBONE bus interface, the use of Verilog to complete. Can simultaneously connect up to 8 masters and 16 slaves.
Update : 2024-05-09 Size : 654336 Publisher : 陶宇
【VHDL-FPGA-Verilog】 led_driver DL : 0: LED display verilog code. to generate clocks and wishbone interface
Update : 2024-05-09 Size : 2048 Publisher : r_ansal
【VHDL-FPGA-Verilog】 AHB_to_Wishbone_Verilog DL : 0: 该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
Update : 2024-05-09 Size : 2077696 Publisher : jinjin
【VHDL-FPGA-Verilog】 wb_conbus DL : 0: wishbone的verilog代码的实现，标准的协议规范-wishbone of the verilog code implementation, the standard protocol specification
Update : 2024-05-09 Size : 20480 Publisher : 蔡搏
【VxWorks】 wbspec_b4 DL : 0: wishbone总线的规范介绍，很详细，很不错-wishbone bus specification describes, in great detail, very good
Update : 2024-05-09 Size : 963584 Publisher : 蔡搏
【VHDL-FPGA-Verilog】 wishbone DL : 0: wishbone协议，IC设计必备 -wishbone agreement, IC design IC design must have the necessary
Update : 2024-05-09 Size : 803840 Publisher : 诸葛龙
【SCM】 wb_flash_latest.tar DL : 0: its a flash controller which is compatable with wishbone
Update : 2024-05-09 Size : 2048 Publisher :
【VHDL-FPGA-Verilog】 Digipot_wb_interface DL : 0: Generic Wishbone Slave interface for AD5204 driver. Instantiable in any platform.
Update : 2024-05-09 Size : 3072 Publisher : Marc
【SCM】 i2c_latest[1].tar DL : 0: I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Master Core provides an interface between a Wishbone Master and an I2C bus.
Update : 2024-05-09 Size : 1479680 Publisher : zhong
【Software Engineering】 WISHBONE DL : 0: WISHBONE片上系统互联总线结构规范-WISHBONE System-on-chip interconnect bus architecture specification
Update : 2024-05-09 Size : 2370560 Publisher : 何某
【VHDL-FPGA-Verilog】 uart_wb DL : 0: 兼容wishbone bus的uart模块，方便用户修改，时候初学者学习-Compatible with wishbone bus the uart module, user-friendly changes beginners to learn when
Update : 2024-05-09 Size : 196608 Publisher : hu

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