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【Other】 wb_master DL : 0: this the wishbone master interface to connect with wishbone slave and a clock module-this is the wishbone master interface to connect with wishbone slave and a clock module
Update : 2024-05-08 Size : 1024 Publisher : Duy
【VHDL-FPGA-Verilog】 IIC_verilog DL : 0: IIC控制器，源代码verilog,WISHBONE总线-IIC controllers, the source code verilog
Update : 2024-05-08 Size : 11264 Publisher : 晨光
【VHDL-FPGA-Verilog】 SPI-SourceCode DL : 0: SPI Serial Peripheral Interface WISHBONE Controller SourceCode
Update : 2024-05-08 Size : 489472 Publisher : horacedu
【VHDL-FPGA-Verilog】 wb_uart_latest.tar DL : 0: 实现一个一16750/16550 UART。该UART内核是完全基于另一个OpenCores的项目：UART_16750塞巴斯蒂安维特。请找到有关于UART内核的文档。该接口是现在有8位Wishbone总线兼容。随着GHDL模拟器只需运行： ./ghdl_uart.bat 使用任何其他模拟器，开始模拟以下perl脚本必须运行之前： uart_test_stim.pl> FILENAME.TXT 其中，FILENAME.TXT是通用的“stim_file”选择内部wb8_uart_transactor.vhd的名称。正确的模拟应退出并断言消息“模拟END”。-Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt. Please find there the documentation regarding the Uart core. The interface is now compatible with a 8-bit WishBone bus. With GHDL simulator simply run: ./ghdl_uart.bat Using any other simulator, before starting the simulation the following perl script must be run: uart_test_stim.pl > filename.txt where filename.txt is the name selected in generic stim_file inside wb8_uart_transactor.vhd. A correct simulation should exit with an assertion message simulation END .
Update : 2024-05-08 Size : 21504 Publisher : 包
【Other】 openmips DL : 0: 一个开源mips处理器verilog 源码-wishbone interface wishbone interface
Update : 2024-05-08 Size : 34816 Publisher : qinfenwoniu
【Other】 draw_wishbone DL : 0: draws a car with a double wishbone suspension geometry
Update : 2024-05-08 Size : 1024 Publisher : anfeenee
【Audio program】 ima_adpcm_encoder_latest.tar DL : 0: This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1.
Update : 2024-05-08 Size : 23552 Publisher : Joe
【VHDL-FPGA-Verilog】 gpio-master DL : 0: 基于WISHBONE总线接口的GPIO模块verilog代码实现，包含详细GPIO定义文档，testbench，RTL仿真与综合环境-WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
Update : 2024-05-08 Size : 419840 Publisher : lv
【VHDL-FPGA-Verilog】 uart16550_latest.tar DL : 0: UART16550是16550兼容的UART核心（主要）。总线接口是WISHBONE SoC总线启。B. 所有功能的标准选择16550 UART：FIFO的基础操作，要求和其他中断。数据表可以下载从CVS树随着源代码-uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded the CVS tree along with the source code
Update : 2024-05-08 Size : 1545216 Publisher : asdtgg
【VHDL-FPGA-Verilog】 graphicallcd_latest.tar DL : 0: 这个核心用于向图形LCD提供符合叉骨的接口。目前它支持基于KS0108B控制器的Crystalfontz CFAG12864系列。 -This core is used to provide a wishbone compliant interface to a graphical LCD. Currently it supports the Crystalfontz CFAG12864 family which is based on the KS0108B controller.
Update : 2024-05-08 Size : 11264 Publisher : asdtgg
【Communication】 4NandFlash.tar DL : 0: nandflash接口的verilog代码，用verilog编写，片上系统SOC源代码分析的nandflash接口代码，总线是wishbone-Nandflash u63A5 u53E3 u7684verilog u4EE3 u7801 uFF0C u7528verilog u7F16 u5199 uFF0C u7247 u4E0A u7CFB u7EDFSOC u6E90 u4EE3 u7801 u5206 u6790 u7684nandflash u63A5 u53E3 u4EE3 u7801 UFF0C u603B u7EBF u662Fwishbone
Update : 2024-05-08 Size : 2048 Publisher : flychan
【Communication】 5SDRAM.tar DL : 0: SRAM接口的verilog代码，用verilog编写，片上系统SOC源代码分析的SRAM接口代码，总线是wishbone-SRAM u63A5 u53E3 u7684verilog u4EE3 u7801 uFF0C u7528verilog u7F16 u5199 uFF0C u7247 u4E0A u7CFB u7EDFSOC u6E90 u4EE3 u7801 u5206 u6790 u7684SRAM u63A5 u53E3 u4EE3 u7801 UFF0C u603B u7EBF u662Fwishbone
Update : 2024-05-08 Size : 5120 Publisher : flychan
【Communication】 6IIS.tar DL : 0: IIS接口的verilog代码，用verilog编写，片上系统SOC源代码分析的IIS接口代码，总线是wishbone-IIS interface verilog code
Update : 2024-05-08 Size : 5120 Publisher : flychan
【Other】 wishbone_vip DL : 0: WISHBONE VIP IN system verilog
Update : 2024-05-08 Size : 1009664 Publisher : nani426
【ARM-PowerPC-ColdFire-MIPS】 sdram_16bit_latest.tar DL : 0: 这个IP核是一个小型的，简单的SDRAM控制器，用于为16位SDRAM芯片提供32位流水线的二叉树接口。当访问开放行时，读写可以流水线实现完整的SDRAM总线利用率，但是读写之间的切换需要几个周期。(This IP core is that of a small, simple SDRAM controller used to provide a 32-bit pipelined Wishbone interface to a 16-bit SDRAM chip. When accessing open rows, reads and writes can be pipelined to achieve full SDRAM bus utilization, however switching between reads & writes takes a few cycles. The row management strategy is to leave active rows open until a row needs to be closed for a periodic auto refresh or until that bank needs to open another row due to a read or write request. This IP supports supports 4 open active rows (one per bank).)
Update : 2024-05-08 Size : 24576 Publisher : hnzziafyz
【VHDL-FPGA-Verilog】 i2c_wb_wrapper_latest.tar DL : 0: I2C Controller Wishbone Wrapper
Update : 2024-05-08 Size : 13312 Publisher : aprsc7
【Other】 ahb2wishbone_latest.tar DL : 0: AHB to wishbone bridge verilog
Update : 2024-05-08 Size : 10638336 Publisher : Sheth
【VHDL-FPGA-Verilog】 eetop.cn_spi.tar DL : 0: 基于wishbone总线的SPI主设备代码(spi master based on wishbone bus)
Update : 2024-05-08 Size : 247808 Publisher : 说给自己听
【Other】 dma_rtl DL : 0: 该代码实现了一个基于Wishbone总线协议的DMA控制器，由于SOC可集成的模块越来越多，本文设计的DMAC包含了31个可编程的DMA通道，能够处理多个DMA传输请求。由于数据在Wishbone总线上传输，在总线接口方面，本文设计的DMAC提供了两个既可以作为主机接口又可以作为从机接口的Wishbone接口。当有多个外设同时发出DMA请求时，本文设计的DMAC采用循环优先级和动态优先级相结合的方式，实现了通道仲裁器二级仲裁的功能。为了提高传输效率，本文设计的DMAC不仅支持数据块的传输，还支持高效的分散/集中DMA传输方式。(In this thesis, after in-depth understanding of Wishbone bus protocol and DMA technology, present a design concept of a DMAC integrated into a Wishbone bus based SOC. The DMAC designed in this thesis contains thirty-one programmable DMA channels, which can handle multiple DMA transfer request. As the data is transmitted over the Wishbone bus, the DMAC provides two Wishbone interfaces that can act as a host interface or as a slave interface. When several peripherals issue DMA transfer request at the same time, the DMAC adopts the combination of cyclic priority and dynamic priority to realize the secondary arbitration function of channel arbiter. In order to improve the transmission efficiency, the DMAC not only supports the transmission of data blocks, but also supports efficient scatter/gather DMA transfer mode.)
Update : 2024-05-08 Size : 74752 Publisher : Tensor_org
【MiddleWare】 wishbone_to_axi4 DL : 0: wishbone to axi4 converter
Update : 2021-08-06 Size : 2648 Publisher : fgnzqiccfbgdvrbltb@bptfp.comfgnzqiccfbgdvrbltb

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