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【VHDL-FPGA-Verilog】 pif2wb_latest.tar DL : 0: This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
Update : 2024-05-08 Size : 2256896 Publisher : Arun
【Embeded-SCM Develop】 wbspec_b3 DL : 0: wishbone接口的规范，wishbone是嵌入式系统中支持的通用接口标准之一-wishbone spec
Update : 2024-05-08 Size : 786432 Publisher : wx
【VHDL-FPGA-Verilog】 pci_bridge DL : 0: 基于WISHBONE的pci桥实现，包括功能模块和测试模块-Based on the pci bridge WISHBONE implementation, including functional modules and test modules
Update : 2024-05-08 Size : 2361344 Publisher : 敬笑
【VHDL-FPGA-Verilog】 i2c_wb_wrapper_latest.tar DL : 0: I2C+Wishbone in VHDL
Update : 2024-05-08 Size : 13312 Publisher : mr_adam
【VHDL-FPGA-Verilog】 SPI_Wishbone_Controller DL : 0: FPGA SPI总线硬件描述语言Verilog下的实现-FPGA SPI bus under the Verilog hardware description language to achieve
Update : 2024-05-08 Size : 199680 Publisher : deng
【Other】 spi_v DL : 0: 基于wishbone总线的spi串口控制器-a spi compilant serial port controller based on wishbone on-chip bus
Update : 2024-05-08 Size : 8192 Publisher : wen
【VHDL-FPGA-Verilog】 a_vhdl_8253_timer_latest.tar DL : 0: 一个用VHDL语言编写的8254定时器。具有一个同步处理器接口比异步的INTEL8254要好-A VHDL 8254 timer，uses a synchronous (Wishbone) processor interface, rather than an asynchronous of the Intel 8254.
Update : 2024-05-08 Size : 107520 Publisher : 赵恒
【VHDL-FPGA-Verilog】 sdcard_mass_storage_controller_latest.tar DL : 0: 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
Update : 2024-05-08 Size : 2271232 Publisher : 张亚群
【VHDL-FPGA-Verilog】 spi_latest[1].tar DL : 0: serial peripheral interface master interface Wishbone compatible
Update : 2024-05-08 Size : 2623488 Publisher : hr
【Other】 yadmc_latest.tar DL : 0: 基于wishbone总线的sdram控制器-sdram control with wishbone interface
Update : 2024-05-08 Size : 21504 Publisher : yangjingjing
【Software Engineering】 wishbone DL : 0: 基于matlab的suspension system 优化-adams suspension system optimization
Update : 2024-05-08 Size : 2064384 Publisher : cairibbon
【ARM-PowerPC-ColdFire-MIPS】 wb_lcd DL : 0: 基于wishbone的字符型lcd core，支持16×2的字符型lcd显示，verilog语言编写-character lcd core based Wishbone bus, support for 16 × 2' s character lcd display, verilog language
Update : 2024-05-08 Size : 1291264 Publisher : 闫江毓
【ARM-PowerPC-ColdFire-MIPS】 8 DL : 0: 基于ADAMS的双横臂独立悬架的仿真分析及优化设计，作者：QQ 64134703 ，欢迎咨询-ADAMS-based double wishbone independent suspension of the simulation analysis and optimization design of: QQ 64134703, welcomed the Advisory
Update : 2024-05-08 Size : 681984 Publisher : 黄永安
【SCM】 166 DL : 0: 基于ADAMS的双横臂独立悬架的仿真,作者：QQ 64134703 ，电子毕业设计，欢迎咨询-ADAMS-based double wishbone independent suspension of the simulation, the author: QQ 64134703, e-graduate design, please consult
Update : 2024-05-08 Size : 681984 Publisher : 黄先生
【SCM】 167 DL : 0: 基于ADAMS的双横臂独立悬架的优化设计,作者：QQ 64134703 ，电子毕业设计，欢迎咨询-ADAMS-based double wishbone independent suspension of the optimal design of: QQ 64134703, e-graduate design, please consult
Update : 2024-05-08 Size : 861184 Publisher : 黄先生
【VHDL-FPGA-Verilog】 miniuart2 DL : 0: 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a PC for data exchange with custom electronic. It was built in the perspective to be very small, but efficient. It had to fit in a small FPGA. It is not suited to interface a modem as there is no control handshaking (CTS/RTS). It integrate two separate clocks, one for wishbone bus, the other for bitstream generation. This has the advantage to let the user bring his own desired frequency for the baudrate.
Update : 2024-05-08 Size : 2588672 Publisher : 李涛
【VHDL-FPGA-Verilog】 zorro_to_wishbone_bridge_latest.tar DL : 0: This project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families, it is intended to support both the Zorro II and Zorro III protocols at the same time on the same bus.
Update : 2024-05-08 Size : 10240 Publisher : amin
【VHDL-FPGA-Verilog】 wbspec_b4.pdf DL : 0: Wishbone interface, for development of system on chip interfaces
Update : 2024-05-08 Size : 968704 Publisher : Ammar
【VHDL-FPGA-Verilog】 ThesummaryofSoCOCB DL : 0: 随着以IP核复用为基础的SoC设计技术的发展，工业界及研究组织积极从事相关IP互联标准方案的制定工作，从目前的研究和发展看，影响力较大的有IBM 公司的CoreConnect、ARM 公司的AMBA 和Silicore Corp公司的Wishbone。基于现有IP互联接口标准技术的发展现状，本文对这三种SoC总线技术进行了详细介绍。-Along with the IP core reuse-based SoC design technology, industry and research organizations actively engaged in programs related to IP connectivity standard setting work, from the current research and development, the impact of the larger companies are IBM CoreConnect , ARM' s AMBA and Silicore Corp' s Wishbone. IP connectivity interface standards based on existing technology, this paper these three SoC bus technology is described in detail.
Update : 2024-05-08 Size : 59392 Publisher : yyj
【VHDL-FPGA-Verilog】 uart_16550 DL : 0: UART是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在嵌入式设计中，UART用来与PC进行通信，包括与监控调试器和其它器件，如EEPROM通信。-A UART that is compatible with the industry standard 16550D includes wrappers for the Wishbone and AMBA APB busses
Update : 2024-05-08 Size : 244736 Publisher : zhaohaiting

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