SPI Serial Peripheral Interface WISHBONE Controller SourceCode

rd1044_spi_controller_with_wishbone_interface
.............................................\rd1044
.............................................\......\docs
.............................................\......\....\rd1044_readme.txt
.............................................\......\....\revision_history.xls
.............................................\......\project
.............................................\......\.......\xo
.............................................\......\.......\..\verilog
.............................................\......\.......\..\.......\xo_verilog.ldf
.............................................\......\.......\..\.......\xo_verilog.lpf
.............................................\......\.......\..\.......\xo_verilog1.sty
.............................................\......\.......\..\vhdl
.............................................\......\.......\..\....\xo_vhdl.ldf
.............................................\......\.......\..\....\xo_vhdl.lpf
.............................................\......\.......\..\....\xo_vhdl1.sty
.............................................\......\.......\xo2
.............................................\......\.......\...\verilog
.............................................\......\.......\...\.......\xo2_verilog.ldf
.............................................\......\.......\...\.......\xo2_verilog.lpf
.............................................\......\.......\...\.......\xo2_verilog1.sty
.............................................\......\.......\...\vhdl
.............................................\......\.......\...\....\xo2_vhdl.ldf
.............................................\......\.......\...\....\xo2_vhdl.lpf
.............................................\......\.......\...\....\xo2_vhdl1.sty
.............................................\......\.......\xo3l
.............................................\......\.......\....\verilog
.............................................\......\.......\....\.......\xo3l_verilog_lse.ldf
.............................................\......\.......\....\.......\xo3l_verilog_lse.lpf
.............................................\......\.......\....\.......\xo3l_verilog_lse1.sty
.............................................\......\.......\....\.......\xo3l_verilog_syn.ldf
.............................................\......\.......\....\.......\xo3l_verilog_syn.lpf
.............................................\......\.......\....\.......\xo3l_verilog_syn1.sty
.............................................\......\.......\....\vhdl
.............................................\......\.......\....\....\xo3l_vhdl_lse.ldf
.............................................\......\.......\....\....\xo3l_vhdl_lse.lpf
.............................................\......\.......\....\....\xo3l_vhdl_lse1.sty
.............................................\......\.......\....\....\xo3l_vhdl_syn.ldf
.............................................\......\.......\....\....\xo3l_vhdl_syn.lpf
.............................................\......\.......\....\....\xo3l_vhdl_syn1.sty
.............................................\......\.......\xp2
.............................................\......\.......\...\verilog
.............................................\......\.......\...\.......\xp2_verilog.ldf
.............................................\......\.......\...\.......\xp2_verilog.lpf
.............................................\......\.......\...\.......\xp2_verilog1.sty
.............................................\......\.......\...\vhdl
.............................................\......\.......\...\....\xp2_vhdl.ldf
.............................................\......\.......\...\....\xp2_vhdl.lpf
.............................................\......\.......\...\....\xp2_vhdl1.sty
.............................................\......\simulation
.............................................\......\..........\xo
.............................................\......\..........\..\verilog
...............................

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