WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn

gpio-master
...........\bench
...........\.....\verilog
...........\.....\.......\clkrst.v
...........\.....\.......\gpio_mon.v
...........\.....\.......\gpio_testbench.v
...........\.....\.......\tb_defines.v
...........\.....\.......\tb_tasks.v
...........\.....\.......\timescale.v
...........\.....\.......\wb_master.v
...........\doc
...........\...\gpio_spec.pdf
...........\...\src
...........\...\...\gpio_spec.doc
...........\rtl
...........\...\verilog
...........\...\.......\gpio_defines.v
...........\...\.......\gpio_top.v
...........\sim
...........\...\rtl_sim
...........\...\.......\bin
...........\...\.......\...\INCA_libs
...........\...\.......\...\.........\worklib
...........\...\.......\...\.........\.......\dir_keeper
...........\...\.......\...\cds.lib
...........\...\.......\...\hdl.var
...........\...\.......\...\rtl_file_list
...........\...\.......\...\sim.sh
...........\...\.......\...\sim_file_list
...........\...\.......\log
...........\...\.......\...\ncelab.log
...........\...\.......\...\ncsim.log
...........\...\.......\...\ncvlog.log
...........\...\.......\run
...........\...\.......\...\ncelab.args
...........\...\.......\...\ncsim.args
...........\...\.......\...\ncsim.tcl
...........\...\.......\...\ncvlog.args
...........\...\.......\...\run_sim
...........\...\.......\...\run_sim_gpio
...........\syn
...........\...\bin
...........\...\...\cons_art_umc18.inc
...........\...\...\cons_vs_umc18.inc
...........\...\...\read_design.inc
...........\...\...\reports.inc
...........\...\...\save_design.inc
...........\...\...\select_tech.inc
...........\...\...\set_env.inc
...........\...\...\tech_art_umc18.inc
...........\...\...\tech_vs_umc18.inc
...........\...\...\top_gpio.scr
...........\...\run
...........\...\...\dodesign

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