A wraper of DDR controller for wishbone bus.

wb_ddr
......\.bzrignore
......\bench
......\.....\lac
......\.....\...\dp_ram.v
......\.....\...\lac.v
......\.....\...\uart.v
......\.....\wb_memtest.v
......\.....\wb_memtest2.v
......\.....\wb_memtest3.v
......\boards
......\......\xilinx-s3esk
......\......\............\Makefile
......\......\............\system.ucf
......\......\............\system.v
......\......\............\system.xst
......\......\............\system_sim.save
......\......\............\system_sim.v
......\doc
......\README
......\rtl
......\...\async_fifo.v
......\...\ddr_clkgen.v
......\...\ddr_ctrl.v
......\...\ddr_include.v
......\...\ddr_init.v
......\...\ddr_pulse78.v
......\...\ddr_rpath.v
......\...\ddr_wpath.v
......\...\dpram.v
......\...\gray_counter.v
......\...\rotary.v
......\...\wb_ddr.v
......\sim
......\...\ddr
......\...\...\ddr.v
......\...\...\ddr_parameters.vh
......\...\...\parameters.v
......\...\...\readme.txt
......\...\unisims
......\...\.......\BUFG.v
......\...\.......\DCM_SP.v
......\...\.......\FDDRRSE.v

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