SoC-Wishbone System IP core language VHDL source code

SoC-Wishbone System IP核的VHDL语言源代码
........................................\System6801
........................................\..........\cpu01
........................................\..........\.....\comp_cpu.do
........................................\..........\.....\cpu01.vhd
........................................\..........\.....\monitor
........................................\..........\.....\.......\cpu01mon.abs
........................................\..........\.....\.......\cpu01mon.hex
........................................\..........\.....\.......\cpu01mon.lst
........................................\..........\.....\.......\cpu01mon.s19
........................................\..........\.....\.......\cpu01mon.sa
........................................\..........\.....\wb_cpu01.vhd
........................................\..........\cyclone_devkit
........................................\..........\..............\wb_cyclone_cpu68.vhd
........................................\..........\ioport
........................................\..........\......\comp_io.do
........................................\..........\......\ioport.vhd
........................................\..........\......\wb_ioport.vhd
........................................\..........\miniUart
........................................\..........\........\acia
........................................\..........\........\....\clkunit.vhd
........................................\..........\........\....\comp_acia.do
........................................\..........\........\....\miniuart.vhd
........................................\..........\........\....\rxunit.vhd
........................................\..........\........\....\txunit.vhd
........................................\..........\........\....\wb_acia.vhd
........................................\..........\........\sci
........................................\..........\........\...\clkunit.vhd
........................................\..........\........\...\miniUART.vhd
........................................\..........\........\...\rxunit.vhd
........................................\..........\........\...\txunit.vhd
........................................\..........\........\...\uart_def.vhd
........................................\..........\........\...\wb_sci.vhd
........................................\..........\rams
........................................\..........\....\comp_rams.do
........................................\..........\....\wb_lpm_ram.vhd
........................................\..........\....\wb_ram.vhd
........................................\..........\roms
........................................\..........\....\comp_roms.do
........................................\..........\....\wb_lpm_rom.vhd
........................................\..........\....\wb_rom.vhd
........................................\..........\system6801
........................................\..........\..........\cpu01
........................................\..........\..........\.....\monitor
........................................\..........\..........\cyclone_devkit
........................................\..........\..........\ioport
........................................\..........\..........\miniUart
........................................\..........\..........\........\acia
........................................\..........\..........\........\sci
........................................\..........\..........\rams
........................................\..........\..........\roms
........................................\使用说明请参看右侧注释====〉〉.txt

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