The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.

camera_cb_calc.v
camera_cr_calc.v
camera_define.v
camera_fifo_ctrl.v
camera_master.v
camera_slave.v
camera_sp_conversion_calc.v
camera_synchronizer_flop.v
camera_sync_ctrl.v
camera_top.v
camera_y_calc.v
cam_master_addr_gen.v
cam_master_fsm.v
clock_divide.v
fifomem.v
format656to601.v
rptr_empty.v
sync_r2w.v
sync_w2r.v
wptr_full.v

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