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WISHBONE_conmax

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-09-03
  • Size : 651kb
  • Downloaded :0次
  • Author :haizi
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Very detailed wishbone bus to learn from the code and documentation
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WISHBONE_conmax
...............\branches
...............\tags
...............\....\start
...............\....\.....\bench
...............\....\.....\.....\verilog
...............\....\.....\.....\.......\test_bench_top.v
...............\....\.....\.....\.......\tests.v
...............\....\.....\.....\.......\wb_mast_model.v
...............\....\.....\.....\.......\wb_model_defines.v
...............\....\.....\.....\.......\wb_slv_model.v
...............\....\.....\doc
...............\....\.....\...\README.txt
...............\....\.....\...\STATUS.txt
...............\....\.....\...\conmax.pdf
...............\....\.....\mast1.pl
...............\....\.....\rtl
...............\....\.....\...\verilog
...............\....\.....\...\.......\wb_conmax_arb.v
...............\....\.....\...\.......\wb_conmax_defines.v
...............\....\.....\...\.......\wb_conmax_master_if.v
...............\....\.....\...\.......\wb_conmax_msel.v
...............\....\.....\...\.......\wb_conmax_pri_dec.v
...............\....\.....\...\.......\wb_conmax_pri_enc.v
...............\....\.....\...\.......\wb_conmax_rf.v
...............\....\.....\...\.......\wb_conmax_slave_if.v
...............\....\.....\...\.......\wb_conmax_top.v
...............\....\.....\sim
...............\....\.....\...\rtl_sim
...............\....\.....\...\.......\bin
...............\....\.....\...\.......\...\Makefile
...............\....\.....\...\.......\run
...............\....\.....\...\.......\...\.nclog
...............\....\.....\...\.......\...\ncwork
...............\....\.....\...\.......\...\......\.cdsvmod
...............\....\.....\...\.......\...\......\.inca.db.134.linux
...............\....\.....\...\.......\...\......\cds.lib
...............\....\.....\...\.......\...\......\hdl.var
...............\....\.....\...\.......\...\......\inca.linux.134.pak
...............\....\.....\...\.......\...\waves
...............\....\.....\...\.......\...\.....\waves.do
...............\....\.....\slv1.pl
...............\....\.....\slv2.pl
...............\....\.....\slv3.pl
...............\....\.....\syn
...............\....\.....\...\bin
...............\....\.....\...\...\.read.dc.swp
...............\....\.....\...\...\comp.dc
...............\....\.....\...\...\design_spec.dc
...............\....\.....\...\...\lib_spec.dc
...............\....\.....\...\...\read.dc
...............\....\.....\txt.pl
...............\....\.....\vim_session.vim
...............\....\.....\x
...............\trunk
...............\.....\bench
...............\.....\.....\verilog
...............\.....\.....\.......\test_bench_top.v
...............\.....\.....\.......\tests.v
...............\.....\.....\.......\wb_mast_model.v
...............\.....\.....\.......\wb_model_defines.v
...............\.....\.....\.......\wb_slv_model.v
...............\.....\doc
...............\.....\...\README.txt
...............\.....\...\STATUS.txt
...............\.....\...\conmax.pdf
...............\.....\rtl
...............\.....\...\verilog
...............\.....\...\.......\wb_conmax_arb.v
...............\.....\...\.......\wb_conmax_defines.v
...............\.....\...\.......\wb_conmax_master_if.v
...............\.....\...\.......\wb_conmax_msel.v
...............\.....\...\.......\wb_conmax_pri_dec.v
...............\.....\...\.......\wb_conmax_pri_enc.v
...............\.....\...\.......\wb_conmax_rf.v
...............\.....\...\.......\wb_conmax_slave_if.v
...............\.....\...\.......\wb_conmax_top.v
...............\.....\sim
...............\.....\...\rtl_sim
...............\.....\...\.......\bin
...............\.....\...\.......\...\Makefile
...............\.....\...\.......\run
...............\.....\...\.......\...\waves
...............\.....\...\.......\...\.....\waves.do
...............\.....\syn
...............\.....\...\bin
...............\.....\...\...\.read.dc.swp
...............\.....\...\...\comp.dc
...............\.....\...\...\design_spec.dc
...............\.....\...\...\lib_spec.dc
...............\.....\...\...\read.dc
...............\web_uploads
...............\...........\conmax.jpg
............
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