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【Embeded-SCM Develop】 sls_sram_16_bit DL : 0: altera NIOS软核系统中构建外接SRAM接口的例子-altera NIOS soft-core system to build external SRAM interface example
Update : 2024-05-20 Size : 3072 Publisher : 黄杰
【VHDL-FPGA-Verilog】 DE2_VGA3 DL : 0: The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine. -The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
Update : 2024-05-20 Size : 1275904 Publisher : Donghua Gu
【ARM-PowerPC-ColdFire-MIPS】 ISPDownload DL : 0: 下载线大全,Xilinx,Altera,ARM,AVR,S52,Lattice-Download Line Book, Xilinx, Altera, ARM, AVR, S52, Lattice
Update : 2024-05-20 Size : 236544 Publisher : 李玉尧
【VHDL-FPGA-Verilog】 ref-sdr-sdram-verilog DL : 0: 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
Update : 2024-05-20 Size : 776192 Publisher : 费尔德
【Software Engineering】 ByteBlasterII_handbook DL : 0: ALTERA下载线原理图，有兴趣的朋友快下载-Download ALTERA line schematic, interested friends fast download
Update : 2024-05-20 Size : 650240 Publisher : wangling
【Other】 EPM7032-7128 DL : 0: altera 公司的EPM7032和EPM7128的DATASHEET-altera s EPM7032 and EPM7128 of DATASHEET
Update : 2024-05-20 Size : 967680 Publisher : joseph
【Other】 CLOCK DL : 0: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Update : 2024-05-20 Size : 182272 Publisher : 张保平
【VHDL-FPGA-Verilog】 AlteraFPGACPLD1 DL : 0: Altera FPGA_CPLD设计基础篇-Altera FPGA_CPLD Part Design
Update : 2024-05-20 Size : 22092800 Publisher : 梁先国
【VHDL-FPGA-Verilog】 Fifo DL : 0: 一个FIFO源代码，基于Altera FPGA-A FIFO source code, based on Altera FPGA
Update : 2024-05-20 Size : 1024 Publisher : jiashengwen
【VHDL-FPGA-Verilog】 Execise DL : 0: altera官方网站上资料的示例代码Quartus II Software Design Series Foundation-altera official website information sample code Quartus II Software Design Series Foundation
Update : 2024-05-20 Size : 18641920 Publisher : jiangwen
【VHDL-FPGA-Verilog】 FPGA_AD DL : 0: 基于Altera的FPGA开发的基于FPGA的AD转换功能，完全通过验证。-Altera s FPGA-based development of FPGA-based AD conversion function, fully validated.
Update : 2024-05-20 Size : 58368 Publisher : sq
【VHDL-FPGA-Verilog】 flash_controller DL : 0: Altera下的FPGA运行Nios处理器的flash控制器-Altera
Update : 2024-05-20 Size : 398336 Publisher : lzm
【Special Effects】 auto_graphics_ref_design-v1.0.4 DL : 0: 基于NIONII的图像获取与真彩屏LCD显示例子，非常好。通过修改可适用于ALTERA的FPGA多个系列。-Based on the image acquisition NIONII color LCD display with real examples, very good. By modifying the applicable ALTERA multiple series of FPGA.
Update : 2024-05-20 Size : 20955136 Publisher : zhanghh624
【VHDL-FPGA-Verilog】 altera_maxII_PCI_Verilog DL : 0: Altera的MAXIICPLD模拟PCI接口的Verilog代码-Altera
Update : 2024-05-20 Size : 106496 Publisher : 王鹏
【VHDL-FPGA-Verilog】 ug_alt_ufm DL : 0: ALTERA公司的MAXⅡ系列CPLD的内部flash使用教程，内容很详细，图文并茂，英文版。-ALTERA s MAX Ⅱ series CPLD to use the internal flash tutorial is very detailed, with illustrations in English.
Update : 2024-05-20 Size : 848896 Publisher : blur
【SCM】 altera_epm1270_MAX DL : 0: 一个ALTERA公司EPM1270 cpld的实验板原理图，其中有PCI接口电路，PDF格式-A ALTERA Corporation EPM1270 cpld schematic diagram of the experimental board, including PCI interface circuit, PDF format
Update : 2024-05-20 Size : 240640 Publisher : blur
【Picture Viewer】 vga_moving_pixel DL : 0: 该项目在VGA显示器上显示一个移动的光点，并且光点的颜色还可以改变。使用VerilogHDL 语言编写，在Altera公司的QuartusII开发环境下验证通过。-The project in the VGA display to show a moving spot, and spot colors can be changed also. VerilogHDL language used in Altera' s development environment QuartusII verification through.
Update : 2024-05-20 Size : 15360 Publisher : submars
【VHDL-FPGA-Verilog】 vga_hex_disp DL : 0: 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。-The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compiling the whole code the user should open mem.v file and change lpm_ram declarations in RAM module and lpm_rom declarations in ROM module into such that are suitable for a particular producer and scheme. There also may appear the necessity of converting .mif files used to memory initialization. The Memory Initialization File is serviced by the Quartus II environment developed by Altera.
Update : 2024-05-20 Size : 18432 Publisher : submars
【Software Engineering】 15Altera_IP DL : 0: 里面包含15个altera的IP核的源代码,包括I2C，UART，VGA_SYN-Which contains 15 nuclear altera the IP source code, including I2C, UART, VGA_SYN
Update : 2024-05-20 Size : 49152 Publisher : hhl
【VHDL-FPGA-Verilog】 a_block_with_several_functions_with_Verilog_HDL.ra DL : 0: Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大，应用硬件描述语言进行描述的CPLD结构，成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计，达到对Verilog HDL的理解，同时对CPLD器件进行简要了解。本文的研究内容包括: 对Altera公司Flex 10K系列的EPF10K 10简要介绍，Altera公司软件Max+plusⅡ简要介绍和应用Verilog HDL对多功能电子钟进行设计。 -Verilog is the most widely used hardware description language.It can be used to the modeling, synthesis, and simulation stages of the hardware system design flow. With the scale of hardware design continually enlarging, describing the CPLD with HDL become the mainstream of designing ASIC and other IC.To comprehend Verilog HDL and get some knowledge of CPLD device, we design a block with several functions with Verilog HDL. This thesis is about to discuss the above there aspects: Introduce the EPF10K 10 of Flex 10K series producted by Altera Corporation simply. the software Max+plusⅡ,Design the block with several functions with Verilog HDL.
Update : 2024-05-20 Size : 482304 Publisher : li

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