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DE2_VGA3

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.22mb
  • Downloaded :0次
  • Author :Donghua Gu
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
Packet file list
(Preview for download)
DE2_VGA3
........\db
........\..\altsyncram_4gp1.tdf
........\..\altsyncram_a5h1.tdf
........\..\DE2_Default.asm.qmsg
........\..\DE2_Default.asm_labs.ddb
........\..\DE2_Default.cbx.xml
........\..\DE2_Default.cmp.cdb
........\..\DE2_Default.cmp.hdb
........\..\DE2_Default.cmp.logdb
........\..\DE2_Default.cmp.qrpt
........\..\DE2_Default.cmp.rdb
........\..\DE2_Default.cmp.tdb
........\..\DE2_Default.cmp0.ddb
........\..\DE2_Default.dbp
........\..\DE2_Default.db_info
........\..\DE2_Default.eco.cdb
........\..\DE2_Default.fit.qmsg
........\..\DE2_Default.hier_info
........\..\DE2_Default.hif
........\..\DE2_Default.map.cdb
........\..\DE2_Default.map.hdb
........\..\DE2_Default.map.logdb
........\..\DE2_Default.map.qmsg
........\..\DE2_Default.pre_map.cdb
........\..\DE2_Default.pre_map.hdb
........\..\DE2_Default.psp
........\..\DE2_Default.rtlv.hdb
........\..\DE2_Default.rtlv_sg.cdb
........\..\DE2_Default.rtlv_sg_swap.cdb
........\..\DE2_Default.sgdiff.cdb
........\..\DE2_Default.sgdiff.hdb
........\..\DE2_Default.sld_design_entry.sci
........\..\DE2_Default.sld_design_entry_dsc.sci
........\..\DE2_Default.smp_dump.txt
........\..\DE2_Default.syn_hier_info
........\..\DE2_Default.tan.qmsg
........\..\decode_1qa.tdf
........\..\mux_akb.tdf
........\..\mux_hkb.tdf
........\DE2_Default.asm.rpt
........\DE2_Default.cdf
........\DE2_Default.done
........\DE2_Default.fit.eqn
........\DE2_Default.fit.rpt
........\DE2_Default.fit.summary
........\DE2_Default.flow.rpt
........\DE2_Default.map.eqn
........\DE2_Default.map.rpt
........\DE2_Default.map.summary
........\DE2_Default.pin
........\DE2_Default.pof
........\DE2_Default.qpf
........\DE2_Default.qsf
........\DE2_Default.qws
........\DE2_Default.sof
........\DE2_Default.tan.rpt
........\DE2_Default.tan.summary
........\DE2_Default.v
........\README.txt
........\Reset_Delay.v
........\talkback
........\........\DE2_Default.asm.talkback.xml
........\........\DE2_Default.fit.talkback.xml
........\........\DE2_Default.map.talkback.xml
........\........\DE2_Default.tan.talkback.xml
........\VGA_Audio_PLL.v
........\VGA_Controller
........\..............\VGA_Audio_PLL.v
........\..............\VGA_Controller.v
........\..............\VGA_Param.h
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