Search - altera

Search - altera - List

【VHDL-FPGA-Verilog】 PWM_LED DL : 0: 基于ALTERA公司NIOSII的LED灯控PWM IP核设计-ALTERA-based company controlled NIOSII the LED lamp PWM IP-core design
Update : 2024-05-20 Size : 10481664 Publisher : 王超
【VHDL-FPGA-Verilog】 LCD_PS2 DL : 0: 基于ALTERA公司的NIOSII的通用TFT-LCD控制器及PS2鼠标设计-NIOSII based on ALTERA' s common TFT-LCD controller and PS2 mouse design
Update : 2024-05-20 Size : 13129728 Publisher : 王超
【VHDL-FPGA-Verilog】 GPS DL : 0: 基于ALTERA公司的NIOSII的GPS信息接收系统的设计-ALTERA company NIOSII based on the GPS receiver system design information
Update : 2024-05-20 Size : 13383680 Publisher : 王超
【VHDL-FPGA-Verilog】 IIC_bus DL : 0: 基于ALTERA公司的NIOSII的I2C总线传输应用设计-NIOSII based on ALTERA s application of the I2C bus transmission design
Update : 2024-05-20 Size : 13466624 Publisher : 王超
【VHDL-FPGA-Verilog】 UART_DMA DL : 0: 基于ALTERA公司的NIOSII的串口通信DMA传输设计-NIOSII based on ALTERA s DMA transfer of the serial communication design
Update : 2024-05-20 Size : 11346944 Publisher : 王超
【VHDL-FPGA-Verilog】 src DL : 0: i2c module. i test it on Altera FPGA.
Update : 2024-05-20 Size : 3072 Publisher : almondeo
【VHDL-FPGA-Verilog】 Altera_DE1_Training_Courses_Multimedia_Platform.zi DL : 0: Altera DE1 多媒体平台训练课程视频教程-Altera DE1 training courses multimedia platform Video tutorial
Update : 2024-05-20 Size : 7545856 Publisher : xiaoxu
【DSP program】 FPGADSPBuilder DL : 0: DE2平台应用及DSPBUILDER技术，是altera杯上海交大电子设计竞赛内部材料，内含详细设计原理及源代码-DE2 platform and DSP BUILDER technology, Shanghai Jiaotong University altera Cup Electronic Design Contest of internal materials, including the principle of the detailed design and source code
Update : 2024-05-20 Size : 3059712 Publisher : lucy
【VHDL-FPGA-Verilog】 jiyu-FPGA-dianziqin DL : 0: 1) 主芯片：Altera 的FLEX10K20TC144-4 STC89C58RD+。 2) 要求扩展键盘接口电路,可以实现电子琴的一般功能，进行乐曲的手动演奏，此外还应该具有存储功能，可以将演奏的乐曲进行存储并在人工控制下进行回放。 3) 完成系统方案设计。 4) 编制相应的VHDL程序并进行相应的仿真工作，完成系统的调试工作。 5) 编写51系统程序，完成初始化、系统控制等功能。 6) 利用51系统实现系统的在线配置。 7) 发挥部分可以进行乐曲的自动演奏。 -1) Main chipset: Altera' s FLEX10K20TC144-4 STC89C58RD+. 2) require the expansion of the keyboard interface circuit can be achieved general organ function, to music performed manually, in addition should have a storage function, which will perform the music store and playback under manual control. 3) complete the system design. 4) the preparation of the corresponding procedures and the corresponding VHDL simulation work, the completion of system testing. 5) procedures for the preparation of 51 systems to complete the initialization, the system control functions. 6) the use of 51 on-line system configuration. 7) to play some music can be performed automatically.
Update : 2024-05-20 Size : 68608 Publisher : 任大志
【VHDL-FPGA-Verilog】 nios DL : 0: altera ep2c8V2 开发实例 timer uart I2C key interrupt 等-altera ep2c8V2 examples timer uart I2C key interrupt etc.
Update : 2024-05-20 Size : 11765760 Publisher : chris
【Software Engineering】 StratixII_NiosII_2S60_DB_Rev01_SCH DL : 0: ALTERA官方StratixII EP2S60ROHS开发板原理图-ALTERA official StratixII EP2S60ROHS development board schematics
Update : 2024-05-20 Size : 422912 Publisher : 王辉
【VHDL-FPGA-Verilog】 AlteraCycloneIIFPGAStarterBoard DL : 0: Altera Cyclone II FPGA Starter Board原理图-Altera Cyclone II FPGA Starter Board Schematic
Update : 2024-05-20 Size : 236544 Publisher : 王辉
【Other】 altera_reed_solomon_design DL : 0: altera 的reed solomn 设计-reed solomn design from altera
Update : 2024-05-20 Size : 576512 Publisher : richard
【VHDL-FPGA-Verilog】 ddr2_hamenc64 DL : 0: VHDL实现的64bit海明码编码模块。可适用于 Xilinx FPGA, Altera FPGA。-VHDL Implement 64 bit Hamming Code (encode)
Update : 2024-05-20 Size : 1024 Publisher : seiya
【VHDL-FPGA-Verilog】 Altera_timing DL : 0: 本文件讲述了Altera的FPGA的时序原理-This document describes Altera' s FPGA timing principle
Update : 2024-05-20 Size : 1533952 Publisher : yeping
【VHDL-FPGA-Verilog】 Splitter DL : 0: Splitter file to be used to split altera avalon st video stream into two avalon st streams.
Update : 2024-05-20 Size : 237568 Publisher : formjk
【VHDL-FPGA-Verilog】 vga2 DL : 0: VHDL code for UP2 board of Altera, that generate a video signal to VGA port.
Update : 2024-05-20 Size : 332800 Publisher : Lokous
【Software Engineering】 SOPC_Nios DL : 0: Altera SOPC Builder 提供了 Nios Ⅱ处理器及一些常用外设接口 ,但并没有提供 12864 液晶模块的接口及驱动。-Altera SOPC Builder provides the Nios Ⅱ peripheral processor and a number of commonly used interface, but did not provide 12864 LCD module and the drive interface.
Update : 2024-05-20 Size : 356352 Publisher : 夏飞
【Software Engineering】 AlteraArticleContestPapers DL : 0: 本源码为Altera中国大学生电子设计文章竞赛的历届获奖论文汇编，内容主题涵盖如下4个方面： PLD在通讯、消费类、计算机和工业控制方面的应用 Altera器件、Quartus® II 软件的设计和优化技术 Altera FPGA在数字信号处理中的应用 Nios® II 软处理器在各领域的应用获奖作品均是是参赛者独立设计的未曾公开发表过的原创性作品，在作品原创性和特色性、实用性（结合当前的热点应用）和作品的完整性（有明确的实验或仿真数）上均有很多优势。每年的获奖论文共18篇左右。-The source code for Altera Chinese Undergraduate Electronic Design Contest of the previous article, the compilation of award-winning paper, which covers four aspects as follows: PLD in the communications, consumer, computer and industrial control applications Altera devices, Quartus ® II software for design and optimization Altera FPGA technology in digital signal processing applications in the Nios ® II soft processor applications in various fields is the award-winning works were designed by participants independence had not been published original works in the works and the characteristics of originality, practical and (combined with the application of the current hot spots) and the integrity of the work (there are clearly a number of experimental or simulation) have many advantages on. The annual award-winning total of 18 papers around.
Update : 2024-05-20 Size : 26785792 Publisher : 成逛
【VHDL-FPGA-Verilog】 Altera_FPGA_pwm DL : 0: 基于FPGA（ALTERA公司的FPGA）PWM的测试程序。-Based on FPGA (ALTERA' s FPGA) PWM test procedures.
Update : 2024-05-20 Size : 2048 Publisher : 王祥以

« 1 2 ... 14 15 16 17 18 1920 21 22 23 24 ... 50 »