NIOSII based on ALTERA s DMA transfer of the serial communication design

UART_DMA
........\cpu_0.v
........\cpu_0_bht_ram.mif
........\cpu_0_dc_tag_ram.mif
........\cpu_0_ic_tag_ram.mif
........\cpu_0_jtag_debug_module.v
........\cpu_0_jtag_debug_module_wrapper.v
........\cpu_0_mult_cell.v
........\cpu_0_ociram_default_contents.mif
........\cpu_0_rf_ram_a.mif
........\cpu_0_rf_ram_b.mif
........\cpu_0_test_bench.v
........\db
........\..\altsyncram_1g22.tdf
........\..\altsyncram_4be1.tdf
........\..\altsyncram_5be1.tdf
........\..\altsyncram_60q1.tdf
........\..\altsyncram_70q1.tdf
........\..\altsyncram_9tl1.tdf
........\..\altsyncram_a422.tdf
........\..\altsyncram_c572.tdf
........\..\altsyncram_cub1.tdf
........\..\altsyncram_e502.tdf
........\..\altsyncram_k1l1.tdf
........\..\altsyncram_n4q1.tdf
........\..\altsyncram_pfn1.tdf
........\..\altsyncram_q8e1.tdf
........\..\altsyncram_r4q1.tdf
........\..\altsyncram_vke1.tdf
........\..\a_dpfifo_8t21.tdf
........\..\a_fefifo_7cf.tdf
........\..\cntr_fjb.tdf
........\..\cntr_rj7.tdf
........\..\decode_aoi.tdf
........\..\ded_mult_2o81.tdf
........\..\dffpipe_93c.tdf
........\..\dpram_5h21.tdf
........\..\dpram_7jd1.tdf
........\..\dpram_9jd1.tdf
........\..\mult_add_4cr2.tdf
........\..\mult_add_6cr2.tdf
........\..\scfifo_1n21.tdf
........\..\UART_DMA.asm.qmsg
........\..\UART_DMA.asm_labs.ddb
........\..\UART_DMA.cbx.xml
........\..\UART_DMA.cmp.cdb
........\..\UART_DMA.cmp.hdb
........\..\UART_DMA.cmp.logdb
........\..\UART_DMA.cmp.rdb
........\..\UART_DMA.cmp.tdb
........\..\UART_DMA.cmp0.ddb
........\..\UART_DMA.cmp2.ddb
........\..\UART_DMA.dbp
........\..\UART_DMA.db_info
........\..\UART_DMA.eco.cdb
........\..\UART_DMA.fit.qmsg
........\..\UART_DMA.hier_info
........\..\UART_DMA.hif
........\..\UART_DMA.map.cdb
........\..\UART_DMA.map.hdb
........\..\UART_DMA.map.logdb
........\..\UART_DMA.map.qmsg
........\..\UART_DMA.pre_map.cdb
........\..\UART_DMA.pre_map.hdb
........\..\UART_DMA.psp
........\..\UART_DMA.pss
........\..\UART_DMA.rtlv.hdb
........\..\UART_DMA.rtlv_sg.cdb
........\..\UART_DMA.rtlv_sg_swap.cdb
........\..\UART_DMA.sgdiff.cdb
........\..\UART_DMA.sgdiff.hdb
........\..\UART_DMA.signalprobe.cdb
........\..\UART_DMA.sld_design_entry.sci
........\..\UART_DMA.sld_design_entry_dsc.sci
........\..\UART_DMA.smp_dump.txt
........\..\UART_DMA.syn_hier_info
........\..\UART_DMA.tan.qmsg
........\dma_0.v
........\jtag_uart_0.v
........\sdram_0.v
........\sdram_0_test_component.v
........\SDRAM_PLL.v
........\sopc_builder_debug_log.txt
........\sram_0.v
........\SRAM_16Bit_512K
........\...............\cb_generator.pl
........\...............\class.ptf
........\...............\hdl
........\...............\...\SRAM_16Bit_512K.v
........\SRAM_16Bit_512K.v
........\System.bsf
........\System.ptf
........\System.ptf.bak
........\System.v
........\System_generation_script
........\System_log.txt
........\System_setup_quartus.tcl
........\System_sim
........\..........\atail-f.pl
........\..........\dummy_file

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