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【VHDL-FPGA-Verilog】 DE2_Synthesizer DL : 1: 利用此源碼可以使用ALTERA DE2開發板將鍵盤變成一部電子琴-Use this source code can use the ALTERA DE2 development board will be turned into an electric piano keyboard
Update : 2024-05-09 Size : 109568 Publisher : 林哲
【VHDL-FPGA-Verilog】 DE2_Web_Server DL : 0: ALTERA DE2開發板一個網路晶片DM9000A的應用範例並將一個網頁嵌入到DE2開發板中-ALTERA DE2 development board DM9000A a network chip and the application example of a web page embedded into the DE2 development board in
Update : 2024-05-09 Size : 2750464 Publisher : 林哲
【Other】 cosine_IP DL : 0: altera 的cosine函数 ip 核-altera the cosine function ip nuclear
Update : 2024-05-09 Size : 2048 Publisher : 李涛
【Embeded-SCM Develop】 i2c_IP DL : 0: altera 的i2c ip核，可直接调用在quartus中把库指向文件位置就可-altera the i2c ip nuclear, can be directly called in the Quartus point in the database file location can be
Update : 2024-05-09 Size : 7168 Publisher : 李涛
【Other】 uart_IP DL : 0: altera 的uart ip核，可直接调用在quartus中把库指向文件位置就可-altera the uart ip nuclear, can be directly called in the Quartus point in the database file location can be
Update : 2024-05-09 Size : 5120 Publisher : 李涛
【Embeded-SCM Develop】 vga_IP DL : 0: altera 的vga ip核，可直接调用在quartus中把库指向文件位置就可-altera the vga ip nuclear, can be directly called in the Quartus point in the database file location can be
Update : 2024-05-09 Size : 2048 Publisher : 李涛
【Other】 de2_vga DL : 0: altera de2开发板上的vga控制器源码-the development of altera de2 board vga controller source
Update : 2024-05-09 Size : 158720 Publisher : 李涛
【MiddleWare】 ram DL : 0: fpga中ram的vhdl的经典程序，适用于ALTERA公司器件-FPGA in VHDL ram the classic procedure, applicable to the company ALTERA devices
Update : 2024-05-09 Size : 1024 Publisher : gcy
【ARM-PowerPC-ColdFire-MIPS】 NIOS_new DL : 0: 基于Altera Cyclone系列FPGA的NIOS II开发板原理图，OrCAD格式-Based on the Altera Cyclone series FPGA-NIOS II development board schematic, OrCAD format
Update : 2024-05-09 Size : 617472 Publisher :
【VHDL-FPGA-Verilog】 15AlteraDEIP DL : 0: 15个Altera的IP的源码.15个Altera的IP的源码-15 Altera s IP source .15 months of Altera s IP source
Update : 2024-05-09 Size : 49152 Publisher : 11
【Software Engineering】 C2H_Training DL : 0: altera 公司的c2h的培训资料c2h_training-altera companies C2H training materials c2h_training
Update : 2024-05-09 Size : 359424 Publisher : guobo
【VHDL-FPGA-Verilog】 H1wQqGvI DL : 0: 详细介绍了ALTERA器件的IP CORE以及如何使用SDR SDRAM CONTROL-Described in detail ALTERA device IP CORE and how to use SDR SDRAM CONTROL
Update : 2024-05-09 Size : 777216 Publisher : 黄辉辉
【Embeded-SCM Develop】 USBBlaster DL : 0: 兼容ALTERA公司的USBBlaster下载线的原理图和PCB文件。非常珍贵，今天割爱了-ALTERA compatible with the company s USBBlaster download line schematic and PCB documents. Very precious, today afford to spare the
Update : 2024-05-09 Size : 1647616 Publisher : 在路上
【Embeded-SCM Develop】 Nios DL : 0: Nios II 处理器中文小册子（altera) NIOS开发板APEX20K版数据手册 niosii资料-软件开发文档北航NIOS教程
Update : 2024-05-09 Size : 7777280 Publisher : 付茗
【ARM-PowerPC-ColdFire-MIPS】 SDRAM DL : 0: ALTERA SDR AM Controller White Paper
Update : 2024-05-09 Size : 658432 Publisher : 付茗
【VHDL-FPGA-Verilog】 i2c_altera DL : 0: I2C总线控制器 altera公司提供VHDL实现代码-I2C bus controller altera companies realize VHDL code
Update : 2024-05-09 Size : 1598464 Publisher : 张庆顺
【VHDL-FPGA-Verilog】 AlteraDE2NET DL : 0: altera公司开发板上关于基于FPGA实现网络协议的硬件描述-altera developed on-board FPGA based on the realization of network protocols, hardware description
Update : 2024-05-09 Size : 538624 Publisher : 张
【VHDL-FPGA-Verilog】 RS422 DL : 0: 这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试-This is a VHDL development with RS422 communication procedures, in the ALTERA FLEX EPF10K passed the test
Update : 2024-05-09 Size : 1586176 Publisher : 徐
【ARM-PowerPC-ColdFire-MIPS】 JTAG DL : 0: This a c_based JATG.This code assumes that you have a JTAG parallel cable connected to your PC // Works with Xilinx parallel III or Altera ByteBlasterMV/
Update : 2024-05-09 Size : 3072 Publisher : xlz
【VHDL-FPGA-Verilog】 DE2_NET DL : 0: Altera的DE2开发板上的DM9000A网络FPGA接口及其驱动程序,还有 Demo程序-Altera
Update : 2024-05-09 Size : 549888 Publisher : 王海江

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