This is a VHDL development with RS422 communication procedures, in the ALTERA FLEX EPF10K passed the test

ycpuRS422
.........\ad.vhd
.........\cmp_state.ini
.........\cpu.asm.rpt
.........\cpu.cdf
.........\cpu.done
.........\cpu.fit.eqn
.........\cpu.fit.rpt
.........\cpu.fit.summary
.........\cpu.flow.rpt
.........\cpu.map.eqn
.........\cpu.map.rpt
.........\cpu.map.summary
.........\cpu.pin
.........\cpu.pof
.........\cpu.qpf
.........\cpu.qsf
.........\cpu.qws
.........\cpu.sim.rpt
.........\cpu.sof
.........\cpu.tan.rpt
.........\cpu.tan.summary
.........\cpu.vhd
.........\cpu.vwf
.........\data_clk.vhd
.........\db
.........\..\add_sub_3nh.tdf
.........\..\add_sub_4sh.tdf
.........\..\add_sub_5sh.tdf
.........\..\add_sub_7nh.tdf
.........\..\add_sub_pqh.tdf
.........\..\add_sub_qqh.tdf
.........\..\add_sub_rqh.tdf
.........\..\add_sub_sqh.tdf
.........\..\cpu.asm.qmsg
.........\..\cpu.cmp.cdb
.........\..\cpu.cmp.ddb
.........\..\cpu.cmp.hdb
.........\..\cpu.cmp.rdb
.........\..\cpu.cmp.tdb
.........\..\cpu.cmp0.ddb
.........\..\cpu.db_info
.........\..\cpu.eco.cdb
.........\..\cpu.eds_overflow
.........\..\cpu.fit.qmsg
.........\..\cpu.hier_info
.........\..\cpu.hif
.........\..\cpu.map.cdb
.........\..\cpu.map.hdb
.........\..\cpu.map.qmsg
.........\..\cpu.pre_map.cdb
.........\..\cpu.pre_map.hdb
.........\..\cpu.psp
.........\..\cpu.rtlv.hdb
.........\..\cpu.rtlv_sg.cdb
.........\..\cpu.rtlv_sg_swap.cdb
.........\..\cpu.sgdiff.cdb
.........\..\cpu.sgdiff.hdb
.........\..\cpu.sim.hdb
.........\..\cpu.sim.qmsg
.........\..\cpu.sim.rdb
.........\..\cpu.sld_design_entry.sci
.........\..\cpu.sld_design_entry_dsc.sci
.........\..\cpu.syn_hier_info
.........\..\cpu.tan.qmsg
.........\..\cpu_cmp.qrpt
.........\do_adc.vhd
.........\do_adc.vwf
.........\exm_self.vhd
.........\exm_self.vwf
.........\generate_int.vhd
.........\generate_int.vwf
.........\gen_1mhz.vhd
.........\gen_1mhz.vwf
.........\get_key_from_rx.vhd
.........\get_key_from_rx.vwf
.........\go_sd_cm.vhd
.........\go_sd_cm.vwf
.........\io.vwf
.........\mainSCAN.vhd
.........\output_file.pof
.........\read_data.vhd
.........\read_pre_set.vhd
.........\read_return_pre_set.vhd
.........\read_return_pre_set.vwf
.........\rx16.vhd
.........\rx16.vwf
.........\rx8.vhd
.........\rx8.vwf
.........\sig_adc.vhd
.........\sig_adc.vwf
.........\timer.vhd
.........\timer.vwf
.........\time_out.vhd
.........\time_out.vwf
.........\tx16.vhd
.........\tx8.vhd
.........\tx8.vwf
.........\writeLED_and_tx.vhd
.........\writeLED_and_tx.vwf

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