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【VHDL-FPGA-Verilog】 seq_gen_576 DL : 0: 高清电视HDTV信号发生器，576P逐行，VHDL语言，ALTERA的Quartus II开发平台-HDTV HDTV signal generator, 576P progressive, VHDL, Altera's Quartus II development platform
Update : 2024-04-28 Size : 161792 Publisher : lidan
【Program doc】 lpm_quick_guide DL : 0: altera公司的fpga期间的所有lpm模块的快速设计，涵盖了全部的lpm ip模块-altera during the fpga all lpm module rapid design, cover all the ip module lpm
Update : 2024-04-28 Size : 532480 Publisher : 江汉
【assembly language】 saa7111_2 DL : 0: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制，将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A/D chip to control the collection, image data are stored in synchronous FIFO- AL422B
Update : 2024-04-28 Size : 1024 Publisher : 古韦剑
【Other】 PCI_Target_ip DL : 0: pci core altera fpga pci开发设计资料-pci core altera fpga development of design information pci
Update : 2024-04-28 Size : 428032 Publisher : zhouhong
【Other】 quartusII_licgen DL : 0: pci core altera fpga pci开发设计资料-pci core altera fpga development of design information pci
Update : 2024-04-28 Size : 156672 Publisher : zhouhong
【Embeded-SCM Develop】 Nios_IPphone DL : 0: 这是基于altera的片上处理器nios 的一个IP电话终端的设计,来源altera的电子设计文章大赛.-This is based on the altera-chip processor Nios an IP telephone terminal design, the source of the electronic design altera article contest.
Update : 2024-04-28 Size : 190464 Publisher : wokkoni
【VHDL-FPGA-Verilog】 FPGApro DL : 0: VERILOG HDL 实际工控项目源码开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2
Update : 2024-04-28 Size : 1228800 Publisher : zc
【Other】 CycloneII_preliminary_fr DL : 0: ALtera FPGA CYCLONE系列的功耗计算工具，相信大家会用的着．-ALtera CYCLONE FPGA series of power calculation tool, I believe we would use to.
Update : 2024-04-28 Size : 96256 Publisher : 喻袁洲
【Other】 NIOStoSOPC DL : 0: 本书主要介绍Altera公司的软核CPU——nios和采用该CPU进行嵌入式系统设计的流程与方法。并以此为着眼点，介绍Altera的片上可编程系统SOPC的设计原理与实践技术，引领读者在低投入的情况下，较快地进入片上系统soc的殿堂。 -This book introduces the Altera s soft-core CPU- nios and the use of the CPU for embedded system design process and methods. As the focus on Altera s programmable system chip SOPC design principle and practice of technology, leading the reader in the case of low-input, fast access to system-on-chip soc hall.
Update : 2024-04-28 Size : 8742912 Publisher : 阿康
【Other】 NiosSystemDesigned_C DL : 0: 本书以Altera公司开发的NIOS嵌入式处理器软核为例，介绍了嵌入式处理器的组成原理和开发应用。介绍NIOS系统设计和c程序编程与调试。-book to Altera NIOS development of the soft-core embedded processor as an example. on the embedded processor's architecture and application development. NIOS introduced c system design and programming and debugging.
Update : 2024-04-28 Size : 7921664 Publisher : 阿康
【Software Engineering】 SOPC_Vidicon DL : 0: 讲述以ALTERA公司的FPGA为核心，基干SOPC技术的嵌入式攒像机的设计-described in the company Altera FPGA as the core, SOPC skeleton embedded bloggers like Machine Design
Update : 2024-04-28 Size : 130048 Publisher : 阿康
【Software Engineering】 altera+dpd DL : 1: 数字预失真在通信领域内IP核的开发文档，包括数学表达式及硬件框图-Digital Predistortion in the field of IP communications in the development of nuclear documents, including mathematical expression and hardware block diagram
Update : 2024-04-28 Size : 1397760 Publisher : 聂华
【VHDL-FPGA-Verilog】 jurbojtag DL : 0: turbo jtag CPLD source code use altera EPM7128S -turbo jtag CPLD source code use altera EPM7 128S
Update : 2024-04-28 Size : 2048 Publisher : z8848
【Other】 DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE) DL : 0: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Update : 2024-04-28 Size : 179200 Publisher : 李中伟
【Other】 ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2024-04-28 Size : 437248 Publisher : kevin
【Crack Hack】 Gerbers_DSP2_REV_C DL : 0: 记算功耗与ALTERA 的高端器件的设计验证-operator credited with the power of Altera's high-end device design certification
Update : 2024-04-28 Size : 1573888 Publisher : 都想风
【Other】 ug_altpll DL : 0: altera公司的IP core，对于初学硬件描述语言，想要利用quartus软件自带的锁相环电路库函数实现自己想要的功能有些帮助-altera the IP core, for hardware description language learning, quartus want to use the software to bring their own PLL circuit to achieve the function they want to help some of the functions
Update : 2024-04-28 Size : 715776 Publisher : 林德
【SCM】 bingxingtongxin DL : 0: 介绍了用ALTERA公司MAX7000系列CPLD芯片实现单片机与PC104ISA总线接口之间的关行通信。给出了系统设计方法及程序源代码。 -introduces the MAX7000 Altera Corporation Series CPLD The position with SCM 04ISA bus interface between the telecommunications firms. Gives the system design and source code.
Update : 2024-04-28 Size : 90112 Publisher : hjgj
【VHDL-FPGA-Verilog】 verilog-som DL : 0: 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
Update : 2024-04-28 Size : 5120 Publisher : 刘索山
【Communication】 Project1-DDS DL : 0: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Update : 2024-04-28 Size : 8192 Publisher : lf

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