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【SourceCode】 altera sdram controller DL : 1: altera sdram controller vhdl
Update : 2011-03-17 Size : 2365413 Publisher : langzhongfeilang@126.com
【Documents】 altera封装 DL : 0: altera产品封装
Update : 2011-04-24 Size : 1810642 Publisher : fengfengff
【Documents】 altera的几种新型的FPGA的配置方法和使用心得.rar DL : 0: altera的几种新型的FPGA的配置方法和使用心得
Update : 2011-05-25 Size : 159242 Publisher : changroc
【Documents】 “Altera杯”第五届全国研究生电子设计竞赛样板 DL : 0: “Altera杯”第五届全国研究生电子设计竞赛样板
Update : 2011-08-29 Size : 896669 Publisher : wsshenjun
【Documents】 altera signalTap逻辑分析仪 DL : 0: Altera.FPGA入门及提高教程]SignalTap.II.逻辑分析
Update : 2011-12-18 Size : 42612594 Publisher : wangzgah@126.com
【SourceCode】 Altera IP Core DL : 0: 15 Altera IP Core
Update : 2012-02-20 Size : 49033 Publisher : mayli8
【Embeded-SCM Develop】 Altera-NIOS32-V220 DL : 0: 一个测试端口测试程序-A test port test procedures
Update : 2024-04-28 Size : 39936 Publisher : 站长
【Embeded-SCM Develop】 verilog实例 [43项] DL : 0: 嵌入式可编程器件CPLD的典型实例压缩包，共计43个源码文件。使用ALTERA的 Muxplus 软件即可编辑仿真相关软件可在教育网ftp下载[天网查询，有很多站点提供]-Embedded Programmable CPLD in a typical example of compressed, for a total of 43 source document. Altera Muxplus use the software can edit simulation software available from the Education Network ftp download [days Web inquiries, many sites provide]
Update : 2024-04-28 Size : 181248 Publisher : 吴旭辉
【Crack Hack】硬件求解平方根 DL : 0: 硬件求解平方根源代码加密 (硬件求解平方根的，将license添加到原有的MaxplusII或QuartusII的license中就可以直接使用，但源代码加密。altera提供 )-solving square root of the hardware encryption code (square root of the hardware solution will be added to the original license MaxplusII or Quartus II of the license which can be directly used, but the source code encryption. ALTERA provide)
Update : 2024-04-28 Size : 39936 Publisher :
【Linux-Unix】 isr_uart_example_code DL : 0: altera串口源代码程序-ALTERA source code procedures
Update : 2024-04-28 Size : 5120 Publisher : 梁远
【Embeded-SCM Develop】 altera DL : 0: FPGA研讨会的一些问题集！-some of the problems set!
Update : 2024-04-28 Size : 398336 Publisher : 林建加
【Documents】 ALTERA FPGA特殊管脚说明 DL : 0: FPGA特殊管脚说明-special note
Update : 2024-04-28 Size : 12288 Publisher : 王进
【VHDL-FPGA-Verilog】 mc8051_cyclone_nios DL : 0: 增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board
Update : 2024-04-28 Size : 2000896 Publisher : 柳如飞
【VHDL-FPGA-Verilog】 tiny16cpu_maxII DL : 0: 这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation
Update : 2024-04-28 Size : 240640 Publisher : 李无志
【VHDL-FPGA-Verilog】 two_d_dct_serial DL : 1: altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码，语言是：verilog 性能不错，不过资源消耗有点大，可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be used to transform learning polynomial algorithm DCT
Update : 2024-04-28 Size : 24576 Publisher : 猪猪
【Embeded-SCM Develop】 perl561src DL : 0: Altera recommends the following system configuration: * Pentium II 400 with 512-MB system memory (faster systems give better software performance) * SVGA monitor * CD-ROM drive * One or more of the following I/O ports: - USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit - Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables - Serial port for MasterBlaster communications cable * TCP/IP networking protocol installed * Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP * Internet Explorer 5.0 or later Memory & Disk Space Requirements USB开发--Altera recommends the following system configuration:* Pentium II 400 with 512-MB system memory (faster systems give better software performance)* SVGA monitor* CD-ROM drive* One or more of the following I/O ports:- USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit- Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables- Serial port for MasterBlaster communications cable* TCP/IP networking protocol installed* Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP* Internet Explorer 5.0 or later Memory & Disk Space Requirements USB development
Update : 2024-04-28 Size : 7300096 Publisher : 周元平
【VHDL-FPGA-Verilog】 sopc DL : 0: altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
Update : 2024-04-28 Size : 8863744 Publisher : 刘吉
【ARM-PowerPC-ColdFire-MIPS】 nios_tutorial DL : 0: altera nois cpu.Very good.
Update : 2024-04-28 Size : 445440 Publisher : 张卫
【VHDL-FPGA-Verilog】 color_bar DL : 0: 使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。-use of the VHDL language ALTERA company's board up3 have vga signal containing a detailed analysis and explanation is a good guide.
Update : 2024-04-28 Size : 10240 Publisher : 石坚
【VHDL-FPGA-Verilog】 altera的IP源码 DL : 0: Altera的IP源码8259，只需打开就能实现-Altera IP source 8259, will be realized only open
Update : 2024-04-28 Size : 149504 Publisher : 王天权

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