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【Other】 AlteraSDRAMControllerWhitePaper DL : 0: Altera SDRAM Controller 白皮书，很详细的文档-Altera SDRAM Controller White Paper, a very detailed document
Update : 2024-04-28 Size : 701440 Publisher : wood
【Embeded-SCM Develop】 SIN_fashengqi DL : 0: 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（DSP）技术，通过在 Nios 中软件编程解决不同的调制方式的实现和选择。系统频率实现 1Hz～20MHz 可调，步进达到了1Hz；完成了调幅、调频、二进制 PSK、二进制 ASK、二进制 FSK 调制和扫频输出的功能。 -2006altera race-based soft-core Nios wide spectrum of sinusoidal signal generator design : Abstract : The use of design-based Nios II embedded processor SOPC technology. Altera Corporation system to the Cyclone FPGA series of digital platform, microprocessor, bus, Digital Frequency Synthesizer, memory and I/O interface hardware concentrated in an FPGA, the use of direct digital frequency synthesis technology and digital modulation waveforms required to achieve the rise, Using FPGA ROM storage of the DDS waveform table, and make full use of on-chip resources, improve the system's accuracy, stability and robustness. Use of new digital signal processing (DSP) technology, Nios through software programming to solve different ways of achieving modulation and choice. Realize the system freq
Update : 2024-04-28 Size : 407552 Publisher : 刘斐
【Other】 ALTERA_byteblastermv_parallel_port_download_cable. DL : 0: ALTERA byteblastermv parallel port download cable-Altera byteblastermv parallel port downl oad cable
Update : 2024-04-28 Size : 191488 Publisher : 梁立林
【VHDL-FPGA-Verilog】 CPLDxiaoche DL : 0: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Update : 2024-04-28 Size : 1024 Publisher : lili
【Software Engineering】 QuartusII_Flow DL : 0: altera公司关于QuartusII操作平台的培训教案，对初学者来说可以受益匪浅-altera QuartusII companies operating platform on the training lesson plans, the newcomer could benefit greatly
Update : 2024-04-28 Size : 3165184 Publisher : achilles
【Embeded-SCM Develop】 pwm_source DL : 0: ALTERA PWM電路這是一個ALTERA的PWM電路，可以整合到NIOSII IDE中，來完成一個PWM的系統。-Altera PWM circuit Altera This is a PWM circuit, NIOSII can be integrated into the IDE, to complete a PWM system.
Update : 2024-04-28 Size : 11264 Publisher : Faye Tung
【Embeded-SCM Develop】 adda_spi DL : 0: 这个源码是用altera公司的开发工具NIOS II IDE开发的基于软核处理器的AD、DA控制程序，通过spi 核控制AD、DA的时序，实现正弦波发送和接收-this source is altera company development tools NIOS II IDE- based soft-core Office JIMMY of AD and DA control procedures, spi nuclear control AD and DA timetables to achieve sine sending and receiving
Update : 2024-04-28 Size : 66560 Publisher : zeng xuan
【Embeded-SCM Develop】 hello_world_0 DL : 0: 此源码是用altera公司的nios II IDE开发的，基于DE2核心板的SD卡播放wav格式音频文件的程序-This source is altera s nios II IDE development, based on the core DE2 board SD card playback wav format audio files
Update : 2024-04-28 Size : 144384 Publisher : zeng xuan
【VHDL-FPGA-Verilog】 8051_nios_vhdl DL : 0: 8051 MCU在nois平台上的实现代码（VHDL），出自Altera公司，经过严格测试核验证-nois 8051 MCU platform in the realization of code (VHDL) from Altera Corporation, after strict verification of nuclear test
Update : 2024-04-28 Size : 102400 Publisher : 钟方
【VHDL-FPGA-Verilog】 8051_nios_doc DL : 0: 8051 MCU在nois平台上实现的说明文档，讲解非常详细，对于设计很有帮助，出自Altera公司。-nois 8051 MCU platform in the realization of documentation to explain in great detail, useful for the design, from Altera Corporation.
Update : 2024-04-28 Size : 134144 Publisher : 钟方
【Other】 altera_avalon_pwm DL : 0: Avalon altera pwm generator. Directly use in SOPC.
Update : 2024-04-28 Size : 1024 Publisher : Davide Merlani
【MPI】 multi_cpu_2c35 DL : 0: altera的fpga设计，包含硬件原理图和软件例程，用nios工具等-altera the FPGA design, contains hardware schematics and software routines, using tools such as Nios
Update : 2024-04-28 Size : 316416 Publisher : how
【Other】 AlteraQuartusII6.0crack DL : 0: Altera Quartus II 6.0 破解文件-Altera Quartus II 6.0 crack documents
Update : 2024-04-28 Size : 6144 Publisher : 王国华
【Com Port】 16450 DL : 0: ALTERA的16450IPCORE能得到源代码的适合古老的芯片可以作为学习参考-the source code will be suitable for the old chip can be used as Learning reference
Update : 2024-04-28 Size : 262144 Publisher : guoyaoming
【Com Port】 8237 DL : 0: ALTERA 8237IPCORE 可以得到源代码的适合初学者学习-Altera 8237IPCORE be source code for beginners learning
Update : 2024-04-28 Size : 279552 Publisher : guoyaoming
【Embeded-SCM Develop】 usb_jtag-20070215-1134 DL : 2: USB JTAG 卡. 允许从主机USB口直接控制JTAG I/O 信号。 USB端与Altera USB-Blaster使用相同的协议。主机端与openwince, OpenOCD和Altera的软件兼容-USB JTAG card. From the mainframe to allow direct USB JTAG control I/O signals. USB terminal and Altera USB-Blaster use the same protocol. And the mainframe-openwince, OpenOCD and Altera software compatibility
Update : 2024-04-28 Size : 100352 Publisher : 张森宁
【Software Engineering】 DSPdesignflow DL : 0: altera的DSP设计流程简介简单介绍了设计框图-altera DSP design flow briefed on the design diagram
Update : 2024-04-28 Size : 18432 Publisher : wangli
【Other】 Quartus_II_7.0_decoder DL : 0: Altera公司的Quartus7.0的lisence 破解程序-Altera's Quartus7.0 the lisence crack procedures
Update : 2024-04-28 Size : 5120 Publisher : sylivian
【VHDL-FPGA-Verilog】 std_cf_1c20 DL : 0: Altera公司开发板1c20 CF卡通用例程（初始化、读、写、测试等）-Altera Corporation development board 1c20 CF cartoon with routines (initialization, reading, writing, testing, etc.)
Update : 2024-04-28 Size : 319488 Publisher : 楚光
【VHDL-FPGA-Verilog】 std_cf_1s40 DL : 0: Altera公司开发板1s40 CF卡通用例程（初始化、读、写、测试等）-Altera Corporation development board 1s40 CF cartoon with routines (initialization, reading, writing, testing, etc.)
Update : 2024-04-28 Size : 236544 Publisher : 楚光

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