Altera Corporation development board 1s40 CF cartoon with routines (initialization, reading, writing, testing, etc.)

std_cf_1s40
...........\button_pio.v
...........\cf.v
...........\cpu.ocp
...........\cpu.v
...........\cpu_jtag_debug_module.v
...........\cpu_jtag_debug_module_wrapper.v
...........\cpu_mult_cell.v
...........\cpu_ociram_default_contents.mif
...........\cpu_test_bench.v
...........\delay_reset_block.bdf
...........\delay_reset_block.bsf
...........\high_res_timer.v
...........\ic_tag_ram.mif
...........\jtag_uart.v
...........\led_pio.v
...........\onchip_ram_64_kbytes.hex
...........\onchip_ram_64_kbytes.v
...........\reconfig_request_pio.v
...........\reset_counter.bsf
...........\reset_counter.v
...........\rf_ram_a.mif
...........\rf_ram_b.mif
...........\sdram.v
...........\sdram_pll.bsf
...........\sdram_pll.v
...........\sdram_pll_bb.v
...........\sdram_test_component.v
...........\seven_seg_pio.v
...........\sopc_builder_debug_log.txt
...........\standard.bdf
...........\standard.pin
...........\standard.qpf
...........\standard.qsf
...........\std_1s40.bsf
...........\std_1s40.ptf
...........\std_1s40.v
...........\std_1s40_setup_quartus.tcl
...........\sysid.v
...........\sys_clk_timer.v
...........\uart1.v

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