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【Other】 xapp858[1] DL : 0: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input/Solution Series (ISERDES) and serial output/Solution Series (O Legacy) function.
Update : 2024-05-19 Size : 296960 Publisher : mingming
【VHDL-FPGA-Verilog】 CommandResponse DL : 0: verilog语言写的sdram控制器—命令响应模块代码，经过测试，逻辑正确，可编译，可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
Update : 2024-05-19 Size : 1024 Publisher : hanjian
【DSP program】 SEEDVPM642_D1 DL : 0: DM642开发板自带，包括音频，视频，SDRAM，UART等，此为其中之一。-DM642 development board to bring their own, including audio, video and SDRAM, UART, this is one of them.
Update : 2024-05-19 Size : 324608 Publisher : 赵钱孙
【DSP program】 SEEDVPM642_eeprom DL : 0: DM642开发板自带，包括音频，视频，SDRAM，UART等，此为其中之一。-DM642 development board to bring their own, including audio, video and SDRAM, UART, this is one of them.
Update : 2024-05-19 Size : 54272 Publisher : 赵钱孙
【DSP program】 DM642memory DL : 0: 测试DSP6400中SDRAM的程序。帮助大家了解DSP6400的存储器资源和调试CCS的过程.-SDRAM DSP6400 testing procedures. To help us all understand the DSP6400 memory resources and CCS debugging process.
Update : 2024-05-19 Size : 44032 Publisher : 聂晟楠
【VHDL-FPGA-Verilog】 FIFO_BEFORE DL : 0: 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
Update : 2024-05-19 Size : 211968 Publisher : eva
【VHDL-FPGA-Verilog】 my_fifo_vhdl DL : 0: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Update : 2024-05-19 Size : 19456 Publisher : 朱效志
【ARM-PowerPC-ColdFire-MIPS】 Init_SDRAM DL : 1: AT91RM9200 SDRAM初始化脚本文件，ADS1.2使用，SDRAM为三星K4S641632E，使用脚本后可以将代码直接通过JTAG下载到SDRAM中，在SDRAM中进行仿真调试，启动文件不要进行修改直接可以使用，同时打开CP15的指令缓存和数据缓存-AT91RM9200 SDRAM initialization script file, ADS1.2 use, Samsung K4S641632E of SDRAM, After using a script code can be downloaded directly through the JTAG of SDRAM, SDRAM conducted in simulation tests, startup files will not amend can be used directly, CP15 opened at the same time the directive cache and data cache
Update : 2024-05-19 Size : 15360 Publisher : Tony
【Embeded-SCM Develop】 AN-SDRAM_SAM7SE_software_example DL : 0: 在用IAR开发AT91SAMSE系列中外扩sdram的源码。-IAR used in the development of a series of foreign expansion AT91SAMSE sdram the source.
Update : 2024-05-19 Size : 373760 Publisher :
【MPI】 SRAM_2 DL : 0: FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序-FPGA SDRAM controller source FPGA SDRAM controller source
Update : 2024-05-19 Size : 553984 Publisher : zlw
【VHDL-FPGA-Verilog】 sdr_sdram DL : 0: 详细的SDRAM控制器HDL代码，最顶层代码，很清晰-detailed SDRAM controller HDL code top-level code, it was very clear
Update : 2024-05-19 Size : 3072 Publisher : 陈建勇
【VHDL-FPGA-Verilog】 sdr_data_path DL : 0: SDRAM控制器Verilog员代码，数据链路模块，完成和顶层模块的数据交换-SDRAM controller member Verilog code, data link module, Top module completed and the data exchange
Update : 2024-05-19 Size : 2048 Publisher : 陈建勇
【VHDL-FPGA-Verilog】 control_interface DL : 0: SDRAM控制器Verilog员代码，控制接口模块，完成和顶层模块的控制命令的传递-SDRAM controller member Verilog code control interface module, Top module and complete the transfer of control orders
Update : 2024-05-19 Size : 3072 Publisher : 陈建勇
【VHDL-FPGA-Verilog】 Commandinterface DL : 0: SDRAM控制器Verilog员代码，命令生成模块，完成SDRAM控制接口命令的生成-SDRAM controller member Verilog code, order generation module, SDRAM interface complete control orders Generation
Update : 2024-05-19 Size : 7168 Publisher : 陈建勇
【Multimedia Develop】 VBuffer_1c6 DL : 0: 视频采集并锁存到SDRAM中的完整代码，运行环境为QII，VHDL与标准参数宏模块调用混合设计　是学习视频采集的很好的参考-Video Capture SDRAM and latches to the integrity code, the operating environment for QII. VHDL standard parameter-called hybrid module is designed to study the Video Capture good reference
Update : 2024-05-19 Size : 4133888 Publisher : 刘留
【Other Embeded program】 9200usb_host_device DL : 0: AT91RM9200的USB host和USB device的代码ADS1.2. USB-Device测试程序: 因为程序运行在SDRAM中，所以要先初始化SDRAM（可用basic boot程序初始，之后不能复位或断电），再运行此程序，程序运行后连接USB端口，计算机会提示检测到新硬件，安装硬件驱动程序atmusb6119.inf 后计算机会把USB端口虚拟为一个串行的端口使用-AT91RM9200 the USB host and USB device code ADS1.2.USB-Device test procedure: Because the procedure is running in SDRAM, and so we have to initialize SDRAM (available for the initial basic boot procedure, followed by Can not reset or power off), then Run this program, the program to run after connecting USB port, the computer will be prompted to detect the new hardware, installing hardware drivers after the computer will atmusb6119.inf virtual USB port to a serial port to use
Update : 2024-05-19 Size : 803840 Publisher : 啊非
【MiddleWare】 leon3-altera-ep2s60-sdr DL : 0: ahb sdram interface.arm cpu series,include controller
Update : 2024-05-19 Size : 98304 Publisher :
【VHDL-FPGA-Verilog】 DDRSDRAM DL : 0: DDR sdram 包含的完整的源码,仿真的相关文件-DDR sdram contains complete source code, simulation of the relevant documents
Update : 2024-05-19 Size : 1021952 Publisher : 飞翔
【Other】 SRDSDRAM DL : 0: SRD SDRAM的介绍文档，里面有比较详细的介绍阿，包括时序-SRD SDRAM introduce the document, which has a more detailed introduction Afghanistan, including the timing
Update : 2024-05-19 Size : 701440 Publisher : 飞翔
【VHDL-FPGA-Verilog】 ddr DL : 0: ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
Update : 2024-05-19 Size : 1022976 Publisher : yuling

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