ISE MIG1.6 generated DDR SDRAM controller code (including TESHBENCH)

ddr
...\ddr.cgp
...\mem_interface_top_withouttb
...\...........................\datasheet.txt
...\...........................\docs
...\...........................\....\adr_cntrl_timingsheet_0.xls
...\...........................\....\read_timingsheet_0.xls
...\...........................\....\write_timingsheet_0.xls
...\...........................\....\xapp701.pdf
...\...........................\....\xapp709.pdf
...\...........................\log.txt
...\...........................\mem_interface_top_xmdf.tcl
...\...........................\mig.prj
...\...........................\par
...\...........................\...\ise_flow.bat
...\...........................\...\mem_interface_top.ucf
...\...........................\...\mem_interface_top.ut
...\...........................\...\README.txt
...\...........................\...\xst_run.txt
...\...........................\rtl
...\...........................\...\mem_interface_top.vhd
...\...........................\...\mem_interface_top_backend_fifos_0.vhd
...\...........................\...\mem_interface_top_controller_iobs_0.vhd
...\...........................\...\mem_interface_top_data_path_0.vhd
...\...........................\...\mem_interface_top_data_path_iobs_0.vhd
...\...........................\...\mem_interface_top_data_tap_inc.vhd
...\...........................\...\mem_interface_top_data_write_0.vhd
...\...........................\...\mem_interface_top_ddr_controller_0.vhd
...\...........................\...\mem_interface_top_idelay_ctrl.vhd
...\...........................\...\mem_interface_top_infrastructure.vhd
...\...........................\...\mem_interface_top_infrastructure_iobs_0.vhd
...\...........................\...\mem_interface_top_iobs_0.vhd
...\...........................\...\mem_interface_top_parameters_0.vhd
...\...........................\...\mem_interface_top_pattern_compare8.vhd
...\...........................\...\mem_interface_top_RAM_D_0.vhd
...\...........................\...\mem_interface_top_rd_data_0.vhd
...\...........................\...\mem_interface_top_rd_data_fifo_0.vhd
...\...........................\...\mem_interface_top_rd_wr_addr_fifo_0.vhd
...\...........................\...\mem_interface_top_tap_ctrl_0.vhd
...\...........................\...\mem_interface_top_tap_logic_0.vhd
...\...........................\...\mem_interface_top_top_0.vhd
...\...........................\...\mem_interface_top_user_interface_0.vhd
...\...........................\...\mem_interface_top_v4_dm_iob.vhd
...\...........................\...\mem_interface_top_v4_dqs_iob.vhd
...\...........................\...\mem_interface_top_v4_dq_iob.vhd
...\...........................\...\mem_interface_top_wr_data_fifo_16.vhd
...\...........................\sim
...\...........................\...\ddr.v
...\...........................\...\ddr1_test_tb.v
...\...........................\...\ddr_parameters.v
...\...........................\...\glbl.v
...\...........................\...\Readme.txt
...\...........................\synth
...\...........................\.....\ddr_v4.sdc
...\...........................\.....\mem_interface_top.lso
...\...........................\.....\mem_interface_top.prj
...\...........................\.....\mem_interface_top.sdc
...\...........................\.....\mem_interface_top_dcm_constraints.sdc
...\...........................\.....\script.tcl
...\mem_interface_top_withtb
...\........................\datasheet.txt
...\........................\docs
...\........................\....\adr_cntrl_timingsheet_0.xls
...\........................\....\read_timingsheet_0.xls
...\........................\....\write_timingsheet_0.xls
...\........................\....\xapp701.pdf
...\........................\....\xapp709.pdf
...\........................\log.txt
...\........................\mem_interface_top_xmdf.tcl
...\........................\mig.prj
...\........................\par
...\........................\...\ise_flow.bat
...\........................\...\mem_interface_top.ucf
...\........................\...\mem_interface_top.ut
...\......

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