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【Parallel Port】 mt48lc2m32b2 DL : 0: the verilog model of sdram-mt48lc2m32b2 device.-the verilog model of sdram- mt48lc2m32b2 d evice.
Update : 2024-05-07 Size : 6144 Publisher : nightyboy
【DSP program】 DSP-I2S-DMA DL : 0: TI DSP TMS320VC5509A的SDRAM、I2S、DMA等的接口程序。-TI DSP TMS320VC5509A of SDRAM, I2S, DMA interface procedures.
Update : 2024-05-07 Size : 41984 Publisher : 刘虹
【VHDL-FPGA-Verilog】 mt48lc8m16a2 DL : 0: sdram的行为级模拟模块,可以模拟一个sdram,用于仿真对sdram的控制.-sdram behavioral simulation module can simulate a sdram. Simulation for the control of sdram.
Update : 2024-05-07 Size : 6144 Publisher : hxwf801
【VHDL-FPGA-Verilog】 sdram_control DL : 0: 这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
Update : 2024-05-07 Size : 339968 Publisher : 李伟
【VHDL-FPGA-Verilog】 sdr_c_trl_verilog DL : 0: SDRAM 控制器的Verilog代码经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
Update : 2024-05-07 Size : 12288 Publisher : 曹大壮
【Other Embeded program】 Demo_ST44B0X DL : 0: 44binit.s ----- 初始化中断、存储器、堆栈等，进行系统初始化，建立C程序运行环境。 memcfg.inc ----- 定义存储器延时、SDRAM配置等参数 option.inc ----- 定义系统时钟频率等 main.c ----- 系统主程序（Main函数等） 44blib.c ----- IO端口初始化、延时和异步串口通讯等基本子程序-44binit.s----- initialization interrupt, memory, stack, for system initialization and establish procedures C runtime environment. Memcfg.inc----- definition of memory delay, SDRAM configuration parameters option.inc----- definition of system clock frequency main.c----- system main program (Main function etc.) 44blib.c----- IO port initialization. Delay and asynchronous serial communications, and other basic subroutine
Update : 2024-05-07 Size : 1454080 Publisher : 张锡良
【DSP program】 TI55sdram DL : 0: TI55系列DSP的EMIF开发中SDRAM的开发配置例程-TI55 series DSP Development SDRAM EMIF the development configuration routines
Update : 2024-05-07 Size : 140288 Publisher : 吕晓明
【Other】 AlteraSDRAMControllerWhitePaper DL : 0: Altera SDRAM Controller 白皮书，很详细的文档-Altera SDRAM Controller White Paper, a very detailed document
Update : 2024-05-07 Size : 701440 Publisher : wood
【Other】 xilinxSynthesizableHighPerformanceSDRAMController. DL : 0: xilinx的SDRAM控制器的白皮书，很详细的-xilinx SDRAM controller of the White Paper, detailed
Update : 2024-05-07 Size : 68608 Publisher : wood
【VHDL-FPGA-Verilog】 sdram_verilog DL : 0: 这是使用VERILOG语言，基于MICRON公司的SDRAM开发的SDRAM接口逻辑-verilog This is the use of language, MICRON-based company's development of the SDRAM SDRAM interface logic
Update : 2024-05-07 Size : 414720 Publisher :
【DSP program】 64SDRAM DL : 0: c64xx系列DSP的sdram测试程序-c64xx Series DSP sdram test procedures
Update : 2024-05-07 Size : 430080 Publisher : 严键
【File Format】 DDR_SDRAM_use_in_embedded DL : 0: 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and high-speed data acquisition, and so on the embedded system, Cache require large amounts of data. DDR (Double Data Rate, double-data rate) SDRAM due to its speed, large capacity, and their prices are cheaper, it can be a very good occasion to meet these massive data cache demand. But DDR SDRAM interface directly with today's microprocessor and DSP memory interface connected, During the need to insert controller microprocessor or DSP memory of the control.
Update : 2024-05-07 Size : 237568 Publisher : joucan
【DSP program】 DEC6713_SDRAM DL : 0: DSP的SDRAM调试的c源程序，开发板自带的，感兴趣的可-DSP SDRAM testing c source development to bring their own plates, be interested to s
Update : 2024-05-07 Size : 165888 Publisher : 刘家兵
【DSP program】 bf533sdram DL : 0: ADI公司Blackfin系列DSP BF533读取SDRAM数据-ADI Blackfin BF533 Series DSP data read SDRAM
Update : 2024-05-07 Size : 67584 Publisher : andysj1982
【Other】 lattice_sdram_source_code DL : 0: lattice sdram 控制器的源码，VHDL语言编码包括仿真文件-lattice sdram controller source code, including VHDL simulation document coding
Update : 2024-05-07 Size : 31744 Publisher : dido wang
【Software Engineering】 2006317163710945 DL : 1: 本文主要解决在VXI总线模块上实现大容量动态存储器的技术难题，介绍了利用可编程逻辑器件实现数字信号处理器（DSP）与同步动态存储器（SDRAM）之间的数据读取逻辑的设计、编程思想，以及必要的硬件连接，编程方法等。-this paper to resolve the VXIbus module to achieve dynamic memory capacity of technical difficulties, introduced to the use of programmable logic devices digital signal processor (DSP) and synchronous dynamic RAM (SDRAM ) reading of data between logic design, programming ideas, and the necessary connecting hardware, programming methods.
Update : 2024-05-07 Size : 17408 Publisher : xcs
【DSP program】 sdram_5509 DL : 0: 5509DSP对外部存储设备SDRAM进行设置并能成功进行访问-5509DSP right SDRAM external storage device can be set up and conducted successful visit
Update : 2024-05-07 Size : 17408 Publisher : margie
【VHDL-FPGA-Verilog】 SDRAM_HY57V6416ET DL : 0: 现代的4bank*1M*16bit的SDRAM（HY57V6416ET）的VHDL行为仿真程序-modern 4bank 1M** 16bit of SDRAM (HY57V6416ET) VHDL simulation program acts
Update : 2024-05-07 Size : 14336 Publisher : 王森
【Documents】 core_2410 DL : 0: 本文详细介绍了S3C2410CPU的引脚分布还有内部SDRAM和NOR FLASH的连线情况-paper describes in detail the distribution of the pin S3C2410CPU there are internal SDRAM and NOR F LASH is the Connection
Update : 2024-05-07 Size : 59392 Publisher : songwenjuan
【source in ebook】 mt48lc4m32b2 DL : 0: mt48lc4m32b2.v 是128M sdram 中典型设计。。可以借鉴。-mt48lc4m32b2.v 128M sdram is typical design. . Be used.
Update : 2024-05-07 Size : 8192 Publisher : chenliang

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