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Search - sdram - List
【
VHDL-FPGA-Verilog
】
source
DL : 1
SDRAM通用接口程序,和Altera所给标准一致-SDRAM generic interface procedures, and to the standards by Altera
Update
: 2024-05-19
Size
: 14336
Publisher
:
王并
【
ARM-PowerPC-ColdFire-MIPS
】
shiyan
DL : 0
c6713的源代码,配置ads8364,sdram,flash-c6713 s source code, configuration ads8364, sdram, flash
Update
: 2024-05-19
Size
: 276480
Publisher
:
张海涛
【
VHDL-FPGA-Verilog
】
DDRSDRAM
DL : 0
基于FPGA 实现DDR SDRAM的控制器-FPGA-based realization of DDR SDRAM controller
Update
: 2024-05-19
Size
: 474112
Publisher
:
张宁
【
VHDL-FPGA-Verilog
】
vga_system
DL : 0
FPGA读写SDRAM的实例,可以当作IPcore来添加,非常有价值的的程序。-FPGA examples SDRAM read and write, can be used as IPCore to add, a very valuable process.
Update
: 2024-05-19
Size
: 21392384
Publisher
:
陈泸华
【
Embeded-SCM Develop
】
9260-sdraminittestok
DL : 0
ARM AT9260的一段初始代码,主要是用来测试SDRAM-ARM AT9260 initial section of the code is primarily used for testing SDRAM
Update
: 2024-05-19
Size
: 283648
Publisher
:
caixf
【
VHDL-FPGA-Verilog
】
sdram
DL : 0
一些实用的sdramVHDL编程源码,对算法编程有借鉴意思,可以提供参考。-Programming sdramVHDL some useful source of reference for the meaning of programming algorithm can provide a reference.
Update
: 2024-05-19
Size
: 4096
Publisher
:
胡清泉
【
VHDL-FPGA-Verilog
】
T4_sdram_control
DL : 0
verilog语言 利用FPGA控制SDRAM,相信很多朋友都需要 快下载吧-control FPGA Verilog language use SDRAM, believe that many of my friends need to download it faster
Update
: 2024-05-19
Size
: 19456
Publisher
:
杜菲
【
VHDL-FPGA-Verilog
】
VerilogSDRAMcontry
DL : 0
本文档是一个使用VERILOG语言所讨论的上SDRAM的基本原理!
Update
: 2024-05-19
Size
: 4096
Publisher
:
JP
【
VHDL-FPGA-Verilog
】
DE2_LCM_SRAM_PIC_DISPLAY
DL : 0
NIOS下,将图片显示到液晶屏上去,基于DE2板子的,全硬件实现,现将图片烧到SDRAM,然后可以直接显示到液晶屏。
Update
: 2024-05-19
Size
: 1234944
Publisher
:
刘赛
【
VHDL-FPGA-Verilog
】
sdram_0
DL : 0
SDRAM的Verilog HDL程序,适合DE2开发板,和TRDB-LCM显示器,很好哦-SDRAM procedures of the Verilog HDL for DE2 development board, and TRDB-LCM display, oh well
Update
: 2024-05-19
Size
: 4096
Publisher
:
白雪
【
ARM-PowerPC-ColdFire-MIPS
】
MPC860_UPM
DL : 0
mpc860 upm驱动 SDRAM 初始化-mpc860 upm drives SDRAM initialization
Update
: 2024-05-19
Size
: 16384
Publisher
:
yangjun
【
VHDL-FPGA-Verilog
】
t26a_ibis
DL : 0
ddr sdram 的控制代码,采用VHDL语言书写-ddr sdram control code, the use of VHDL language
Update
: 2024-05-19
Size
: 281600
Publisher
:
zxb
【
VHDL-FPGA-Verilog
】
FaultToleranceTechniquesforSRAMBasedFPGAs
DL : 0
基于FPGA的SDRAM设计,相信大家都会感兴趣!原版的外文书-FPGA-based SDRAM design, I believe we all are interested! Outside the original instrument
Update
: 2024-05-19
Size
: 6116352
Publisher
:
邓振淼
【
Embeded Linux
】
vividriver
DL : 0
s3c2410嵌入式引导程序vivi中的驱动部分,已分成单个的实验,包括mmu、sdram、uart、timer、interrupt等,可按每个实验单独学习一个内容-S3C2410 embedded boot drive vivi in part, has been divided into individual experiments, including mmu, sdram, uart, timer, interrupt, etc., can learn from each experiment a separate content
Update
: 2024-05-19
Size
: 51200
Publisher
:
夸父
【
VHDL-FPGA-Verilog
】
SDR_SDRAM_controler_verilog
DL : 0
可以用的通用SDRAM控制器,可以用在FPGA上,是SDR类型的-Can use the generic SDRAM controller can be used in the FPGA, the SDR is the type of
Update
: 2024-05-19
Size
: 9216
Publisher
:
郑宏超
【
Software Engineering
】
FPGA_SDR_Sdram_LED
DL : 0
针对主控制板上存储器(SRAM) 存储的数据量小和最高频率低的情况,提出了基于SDR Sdram(同步动态RAM) 作为主存储器的LED 显示系统的研究。在实验中,使用了现场可编程门阵列( FPGA) 来实现各模块的逻辑功能。最终实现了对L ED 显示屏的控制,并且一块主控制板最大限度的控制了256 ×128 个像素点,基于相同条件,比静态内存控制的面积大了一倍,验证了动态内存核[7 ]的实用性。-For the main control board memory (SRAM) a small amount of stored data and the highest frequency of low, based on SDR Sdram (Synchronous Dynamic RAM) as the main memory of the LED display systems. In the experiment, the use of field programmable gate array (FPGA) to realize the logic function of each module. The eventual realization of L ED display control, and a master control panel to maximize the control of the 256 × 128 pixels point, based on the same conditions than the static memory control area has doubled, to verify the dynamic memory of nuclear [7 ] the practicality.
Update
: 2024-05-19
Size
: 510976
Publisher
:
郑宏超
【
Other
】
SDRAM-HY57V641620
DL : 0
动态随即存储器的时序和工作原理,剖析了其运行的状态机,对底层程序开发有帮助(例子是关于HY57V641620)-Then the dynamic memory timing and working principle, analyzes the state machine its running on the bottom of program development helpful (example is the HY57V641620)
Update
: 2024-05-19
Size
: 432128
Publisher
:
hlc
【
VHDL-FPGA-Verilog
】
hssdrc.tar
DL : 0
高速SDRAM控制器,并提供仿真测试程序和较详细的文档。-High-speed SDRAM controller, and provide simulation testing procedures and more detailed documents.
Update
: 2024-05-19
Size
: 424960
Publisher
:
yuhl
【
VHDL-FPGA-Verilog
】
347
DL : 0
SDRAM的控制器的VHDL语言编写代码
Update
: 2024-05-19
Size
: 50176
Publisher
:
张彦
【
VHDL-FPGA-Verilog
】
61EDA_C52
DL : 0
标准SDR SDRAM控制器参考设计,有助于大家学习和参考-Standard SDR SDRAM controller reference design will help everyone to learn and reference
Update
: 2024-05-19
Size
: 205824
Publisher
:
王廷龙
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