Search - sdram

Search - sdram - List

【Compress-Decompress algrithms】 rd1010_source_code DL : 0: 使用FPGA做SDRAM控制器 -SDRAM controller using FPGA so
Update : 2024-05-19 Size : 357376 Publisher :
【ARM-PowerPC-ColdFire-MIPS】 mem_ctrl.tar DL : 0: verilog 写的 memory controller ，可以控制SDRAM SRAM NOR -written in Verilog memory controller, can control SDRAM SRAM NOR
Update : 2024-05-19 Size : 331776 Publisher : youjia
【Documents】 dram_rf DL : 0: sdram的详细介绍，详细介绍了sdram的存储机制，以及操作时序-A detailed description of SDRAM, detailing SDRAM memory mechanisms, as well as the operation timing
Update : 2024-05-19 Size : 704512 Publisher : 陈华
【Software Engineering】 P4_PPC_SDRAM_Reference_Design DL : 0: SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM-SDRAM reference design: mainly include The following figure shows a high-level block diagram for this reference design followed by a briefdescription of each sub-section. The design consists of: PowerPC processor PLB-OPB bridge BlockRAM Memory Controller SDRAM Controller Two GPIO ports A UART Port External SDRAM
Update : 2024-05-19 Size : 33792 Publisher : 庞志勇
【VHDL-FPGA-Verilog】 sdram_inf DL : 0: sdram操作的vhdl源代码，对自己编写SDRAM核有很好的参考意义-SDRAM operation of VHDL source code, the preparation of their own nuclear SDRAM have a good reference value
Update : 2024-05-19 Size : 2048 Publisher : 宋军
【VHDL-FPGA-Verilog】 sdram_ctrl.tar DL : 0: SDRAM控制IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SDRAM control IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Update : 2024-05-19 Size : 88064 Publisher : 周华茂
【Software Engineering】 QQ2440 DL : 0: s3c2440的方案包括sdram 网络等protel格式-The program includes S3C2440 SDRAM networks Protel format
Update : 2024-05-19 Size : 125952 Publisher : ydd
【VHDL-FPGA-Verilog】 xapp134_vhdl DL : 0: The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with timing constraints at 115 MHZ.-err
Update : 2024-05-19 Size : 2628608 Publisher : ronsullivan
【SCM】 SCH DL : 0: 44B0嵌入式系统设计与开发完整的原理图，包括Etc，FLASH，jtag_sch，Sdram-44B0 embedded system design and development of a complete schematic diagram, including Etc, FLASH, jtag_sch, Sdram
Update : 2024-05-19 Size : 238592 Publisher : 胡正明
【Embeded-SCM Develop】 sdram DL : 0: Update : 2024-05-19 Size : 35840 Publisher : 郭红梅
【VHDL-FPGA-Verilog】 H1wQqGvI DL : 0: 详细介绍了ALTERA器件的IP CORE以及如何使用SDR SDRAM CONTROL-Described in detail ALTERA device IP CORE and how to use SDR SDRAM CONTROL
Update : 2024-05-19 Size : 777216 Publisher : 黄辉辉
【DSP program】 PLL-SDRAM DL : 0: ADI-BF533 DSP的启动初始化配置源代码-ADI-BF533 DSP startup to configure the source code to initialize
Update : 2024-05-19 Size : 434176 Publisher : wdz
【USB develop】 MyUDisk DL : 0: 这是我学USB时候，在写的s3c2410上实现的一个32M的优盘演示程序。因为主要目的是在学习USB协议，所以U盘的文件内容直接以SDRAM作为存储介质。-This is my USB school when S3C2410 written on a 32M realize the USB demo program. Because the main purpose is to learn from USB protocol, so the contents of the paper U disk directly to SDRAM as storage medium.
Update : 2024-05-19 Size : 129024 Publisher : peizhiluo
【ARM-PowerPC-ColdFire-MIPS】 SDRAM DL : 0: ALTERA SDR AM Controller White Paper
Update : 2024-05-19 Size : 658432 Publisher : 付茗
【Software Engineering】 sdram_papers DL : 0: SDRAM的逻辑Bank与芯片容量表示方法.-SDRAM chip logic Bank with the capacity of representation.
Update : 2024-05-19 Size : 1153024 Publisher : 李飞
【Program doc】 FPGA DL : 0: SDRAM控制模块；图象采集系统说明性稳当；DSP图象采集系统。SDRAM作为存储器。-SDRAM control module image acquisition system illustrative trustworthy DSP image acquisition system. SDRAM as the memory.
Update : 2024-05-19 Size : 179200 Publisher : yan
【VHDL-FPGA-Verilog】 SDRAMconntrol DL : 0: SDRAM控制器的设计与VHDL实现是pdf格式的。在工程中实现过-SDRAM Controller Design with VHDL realize is pdf format. In the projects implemented
Update : 2024-05-19 Size : 138240 Publisher : hjx
【DSP program】 DEC6713 DL : 0: DSP tms320c6713 的EMIF 配置gel文件例子，按此配置DSP能访问外部SDRAM和FLASH，已经过验证。-DSP tms320c6713 the EMIF configuration file example gel, this DSP can configure access to external SDRAM and FLASH, has already been verified.
Update : 2024-05-19 Size : 3072 Publisher : 鲍亚其
【VHDL-FPGA-Verilog】 SDRAMtest DL : 0: SDRAM的读写测试，便于大家深入了解SDRAM的工作原理！-SDRAM read and write tests for our in-depth understanding of the working principle of SDRAM!
Update : 2024-05-19 Size : 156672 Publisher : 张文
【VHDL-FPGA-Verilog】 newsdram DL : 0: 8读8写SDRAM verilog 程序-8 Reading SDRAM verilog to write 8 procedures
Update : 2024-05-19 Size : 2091008 Publisher :

« 1 2 ... 8 9 10 11 12 1314 15 16 17 18 ... 50 »