lattice sdram controller source code, including VHDL simulation document coding

Source
......\CPLD_Verilog
......\............\sdr_5kvg_top.v
......\............\sdr_ctrl.v
......\............\sdr_data.v
......\............\sdr_par.v
......\............\sdr_sig.v
......\............\sdr_top.v
......\EC_Verilog
......\..........\sdr_ctrl.v
......\..........\sdr_data.v
......\..........\sdr_par.v
......\..........\sdr_sig.v
......\..........\sdr_top.v
Testbench
.........\CPLD_Verilog
.........\............\sdr_5kvg_tb.tf
.........\............\sdr_tb.tf
.........\EC_Verilog
.........\..........\sdr_tb.tf

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