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【VHDL-FPGA-Verilog】 PS_2 DL : 0: 此模块用于"PS/2接口的鼠标或键盘"与"具有外部读写的8位并口单片机"双向通信模块. Verilog HDL语言编写,在Quartus II 8.1 (32-Bit)软件中编译,并下载至EPM7128SLC84-10芯片中通过. 文件中有详细的注解. 此模块具有对于PS/2时钟和数据线的滤波功能,这样减少外部干扰，保证通信的可靠性！ -This module for the "PS/2 mouse or keyboard interface" and "read and write with an external parallel port single-chip 8" two-way communication module. Verilog HDL language, in the Quartus II 8.1 (32-Bit) software compiler and downloaded to EPM7128SLC84-10 chip through. document detailed comments. This module has the PS/2 clock and data line filtering, so that to reduce the external interference, and ensure the reliability of communication!
Update : 2024-05-07 Size : 5120 Publisher : yuantielei
【Documents】 niosIIethernetconfig DL : 0: 描述通过软核nios II在quartus环境里面实现以太网卡配置过程，。-Described through the nios II soft-core in the Quartus environment inside Ethernet card configuration process.
Update : 2024-05-07 Size : 268288 Publisher : ami
【VHDL-FPGA-Verilog】 vga_hex_disp DL : 0: 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。-The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compiling the whole code the user should open mem.v file and change lpm_ram declarations in RAM module and lpm_rom declarations in ROM module into such that are suitable for a particular producer and scheme. There also may appear the necessity of converting .mif files used to memory initialization. The Memory Initialization File is serviced by the Quartus II environment developed by Altera.
Update : 2024-05-07 Size : 18432 Publisher : submars
【VHDL-FPGA-Verilog】 newvhdl DL : 0: 在 Quartus II 7.1平台下，用VLDL写的一个计时器的程序-a timer written in VLDL in Quartus II 7.1 platform
Update : 2024-05-07 Size : 72704 Publisher : xwl
【File Format】 QUARTUS_II_compile_and_simulate DL : 0: Verilog HDL 在QUARTUS II下的编译和仿真顺序-Verilog HDL in QUARTUS II compiler and simulation under the order of
Update : 2024-05-07 Size : 1567744 Publisher : 陈阿水
【VHDL-FPGA-Verilog】 VGAdisplay DL : 0: VHDL入门实验。256色VGA显示驱动开发软件Quartus II 6.0 芯片EP2c8Q208-VHDL entry experiment. 256-color VGA display driver development software Quartus II 6.0 chip EP2c8Q208
Update : 2024-05-07 Size : 421888 Publisher : 唐锐
【Other Embeded program】 LCD DL : 0: Quartus, Sopc Builder搭建的CPU，通过NIOS控制LCD。工程文件。-Quartus, Sopc Builder to build the CPU, through the NIOS control LCD. Engineering documents.
Update : 2024-05-07 Size : 2997248 Publisher : 小杨
【VHDL-FPGA-Verilog】 Crack_QII72 DL : 0: 对于quartus 7.2软件进行破解的工具保-For quartus 7.2 crack tools software security
Update : 2024-05-07 Size : 337920 Publisher : mimi
【VHDL-FPGA-Verilog】 word DL : 0: Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own female names: ULA and ALA whose are scrolling on the 4-columns crystal LED. When you press the switch it will turn from ULA into ALA and continue scrolling.
Update : 2024-05-07 Size : 1024 Publisher : Gooreck
【VHDL-FPGA-Verilog】 PLLTEST DL : 0: Altera Quartus to Pll Source
Update : 2024-05-07 Size : 387072 Publisher : Seo Dong hyeok
【Embeded-SCM Develop】 NIOS_LED DL : 0: 完整的Nios 2 演示工程，包括Quartus II 工程和NIOS IDE下的c代码。采用NIOS 2处理器控制LED。已通过实验测试。-Complete Nios 2 demonstration projects, including the Quartus II and NIOS IDE works under the c code. NIOS 2 processor to control the use of LED. Experimental tests have passed.
Update : 2024-05-07 Size : 763904 Publisher : M
【Other】 MATLAB_and_FPGA DL : 0: 附录光盘说明本书附赠的光盘包括各章节实例的设计工程与源码，所有工程在下列软件环境下运行通过： ? Windows XP SP2 ? MATLAB ? Altera Quartus II ? synplify8.4 ? modelsim_ae6.1 光盘目录与实例名称的对应关系如下： cht02文件夹中存放的是书中第2章中的例子，读者可以将一些简单例子的代码拷贝到MATLAB命令窗口进行运行，也可以把一些复杂的例子做成一个单独的*.m文件然后运行、调试(要将每行前的“>>”删除)。 cht04文件夹存放的是书中第4章的例子代码。每个例子都建立了一个单独的文件夹，除了存放与例子相关的代码外，还对各个例子建立了Quartus II工程，编制了仿真测试向量，并对例子进行了编译、综合、布局布线和时序仿真。 cht05文件夹中存放的是一个完整的正弦波频率产生的例子，即书中5.4.1节中的代码，读者可以应用这些代码建立自己的项目，按照书中介绍的方法，获得完整的项目设计经验。注意事项：光盘中的源代码为作者编写，并调试通过，有兴趣的读者可以在此基础上进行二次开发，但请不要用作商业用途。 -CD-ROM Appendix Description The book comes with a CD-ROM includes examples of various sections of the design engineering and source code, all works in the following software environment to run through: ? Windows XP SP2 ? MATLAB ? Altera Quartus II ? Synplify8.4 ? Modelsim_ae6.1 CD-ROM directories and examples of correspondence between the names is as follows: cht02 folders stored in the book are Chapter 2 of the examples, readers may be some simple code examples Copy to the MATLAB command window to run, you can put some examples of the complex into a single And the*. m files to run, debug (to each line before the ">>" delete). cht04 folders stored in the book are examples of Chapter 4 code. Examples of each set up a separate folder, In addition to the storage associated with the example code, but also examples of each set up a Quartus II project, the preparation of the simulation test vectors, and examples have been compiled, integrated, p
Update : 2024-05-07 Size : 6961152 Publisher : 吕成林
【Other】 piano DL : 0: 电子琴，quartus开发环境，硬件连接模型，蜂鸣器-piano
Update : 2024-05-07 Size : 1559552 Publisher : 汪雷明
【VHDL-FPGA-Verilog】 miffile DL : 0: 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
Update : 2024-05-07 Size : 1024 Publisher : 何亮
【VHDL-FPGA-Verilog】 quartus-reading-and-thinking DL : 0: 本资料详细介绍了quartus11的使用方法和使用quartus11进行硬件详细开发流程。-quartus11：simple using the quartus11 sofeware .
Update : 2024-05-07 Size : 6144 Publisher : sunbaoyu
【Other】 EPCS DL : 0: EPCS FPGA Quartus II 编程教程，很好的视频,这个视频教你怎么编程-EPCS FPGA Quartus II
Update : 2024-05-07 Size : 3342336 Publisher : sunlichao
【VHDL-FPGA-Verilog】 FIFO DL : 0: 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
Update : 2024-05-07 Size : 4096 Publisher : 邵捷
【SCM】 16bit_display8bitLED DL : 1: Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. Introduction to use the environment: Quartus II 7.2 SP1+ DE2 (Cyclone II EP2C35F627C6) the use of a simple switch as a binary input 2, and paragraph 8-digit binary display 16 results.
Update : 2024-05-07 Size : 7168 Publisher : 王媛媛
【VHDL-FPGA-Verilog】 Leon_tutorial_Altera_english DL : 0: Leon Altera Boarsds. This shows how to synthesis leon processor to altera boards through the use of quartus 3.-Leon on Altera Boarsds. This shows how to synthesis leon processor to altera boards through the use of quartus 3.
Update : 2024-05-07 Size : 345088 Publisher : wsun013
【VHDL-FPGA-Verilog】 Time DL : 1: 24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
Update : 2024-05-07 Size : 382976 Publisher : 张苏昕

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