a timer written in VLDL in Quartus II 7.1 platform

newvhdl
.......\clkgen1.bsf
.......\clkgen1.vhd
.......\clkgen2.bsf
.......\clkgen2.vhd
.......\cnt10.bsf
.......\cnt10.vhd
.......\cnt6.bsf
.......\cnt6.vhd
.......\db
.......\..\miaobiao.db_info
.......\..\miaobiao.eco.cdb
.......\..\miaobiao.sld_design_entry.sci
.......\displayh.bsf
.......\displayh.vhd
.......\displayl.bsf
.......\displayl.vhd
.......\miaobiao.asm.rpt
.......\miaobiao.bdf
.......\miaobiao.cdf
.......\miaobiao.done
.......\miaobiao.dpf
.......\miaobiao.fit.eqn
.......\miaobiao.fit.rpt
.......\miaobiao.fit.summary
.......\miaobiao.flow.rpt
.......\miaobiao.map.eqn
.......\miaobiao.map.rpt
.......\miaobiao.map.summary
.......\miaobiao.pin
.......\miaobiao.pof
.......\miaobiao.qpf
.......\miaobiao.qsf
.......\miaobiao.qws
.......\miaobiao.sof
.......\miaobiao.tan.rpt
.......\miaobiao.tan.summary
.......\miaobiao_assignment_defaults.qdf
.......\prev_cmp_miaobiao.qmsg
.......\segmain.bsf
.......\segmain.vhd

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