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【VHDL-FPGA-Verilog】 fft_IPcore DL : 0: 这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。
Update : 2024-05-07 Size : 8719360 Publisher : 李杰
【Software Engineering】 QuartusII_lab DL : 0: Quartus II的实验指导。对初学QUQARTUS II 的业内人士适用-Quartus II experimental guidance. For beginner QUQARTUS II applies to the industry
Update : 2024-05-07 Size : 1308672 Publisher : 高大仙
【VHDL-FPGA-Verilog】 qqq DL : 0: 数字滤波器的vhdl源代码.在quartus上运行过,里面还有matlab的仿真文件.-Digital filter of the VHDL source code. In Quartus run-off, along with the simulation matlab file.
Update : 2024-05-07 Size : 26624 Publisher : 萧勇
【Embeded-SCM Develop】 sd_audio_aic23 DL : 0: SD卡和AIC23数字音频输出实验, FreeDev Audio Dsp Board采用了TI公司的TVL320AIC23 1、控制接口使用I2C，Quartus中将CS置低（器件地址0011010）。 2、数字音频接口使用了组件FreeDev_aic23,有三种测试和应用模式，中断结合DMA方式能在NIOS II中采集和发送数据。中断信号产生于模块中FIFO缓冲区的半满信号，读取数据端口自动清除中断请求信号。 3、I2C IP 和FreeDev_aic23 IP分别在Quartus 工程目录中 4、SD卡读写通过SD_DAT0、SD_CLK、SD_CMD三个PIO信号线用软件控制时序。 5、该范例读SD卡数据，通过DMA将Buffer数据送到FreeDev_aic23的 FIFO中实现数据播放。 6、SD卡中的数据必须是以48K*16bit保存的采样数据。数据可以通过SD读卡器写入。
Update : 2024-05-07 Size : 13312 Publisher : HuFengzhang
【Other】 sin DL : 0: Quartus II设计正弦信号发生器。本节通过正弦信号发生器的设计对QuartusII的一些重要功能作一些说明。对本节的详细了解有利于对以后章节有关DSP Builder的应用和设计有更好的理解。-Quartus II design sinusoidal signal generator. This section through the sinusoidal signal generator QuartusII the design of some of the important features to make some notes. Of this section to learn more about the future in favor of the relevant sections of the application of DSP Builder and design have a better understanding.
Update : 2024-05-07 Size : 869376 Publisher : yehui
【Other Embeded program】 Freq DL : 0: 简易数字频率计，用Verilog HDL编写的，基于Quartus II实现，结构清晰，功能较为全面，能满足简单的频率测量要求-Simple digital frequency meter, using Verilog HDL prepared, based on the Quartus II realize, clear structure, function is more comprehensive to meet the simple requirements of frequency measurement
Update : 2024-05-07 Size : 404480 Publisher : 余翔
【Software Engineering】 quartusfft DL : 0: Quartus MegaCore FFT usage. Incluging example.
Update : 2024-05-07 Size : 1131520 Publisher : MyName
【VHDL-FPGA-Verilog】 altera_ram DL : 0: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit.
Update : 2024-05-07 Size : 180224 Publisher : panyouyu
【Documents】 singt_vhdl_quartus DL : 0: 正弦波发生器，可以应用，开发环境QUARTUS,实验箱为GW48-Sine wave generator, can be applied, development environment QUARTUS, experimental box for GW48
Update : 2024-05-07 Size : 891904 Publisher : 在路上
【JSP】 20070102160256236 DL : 0: quartus 的是用教程，很好用的，传上去和大家交流一下-Quartus is to use tutorials, very good use, and Chuan-up and the U.S. exchange
Update : 2024-05-07 Size : 3164160 Publisher : jsh
【matlab】 1 DL : 0: 如何利用Matlab创建Quartus波形仿真文件，很详细-How to use Matlab to create Quartus simulation waveform files, very detailed
Update : 2024-05-07 Size : 5120 Publisher : ylt
【Embeded-SCM Develop】 CF_NiosII5.0 DL : 0: Compact Flash Support For Nios II 5.0, To download supporting materials for this new Compact Flash support, download the following .zip file, extract to a computer with Quartus II 5.0 & Nios II 5.0 installed, and proceed to use the hardware and/or software examples of your choice to proceed. Additional information is available in the readme.txt document, included in the top-level of the .zip file
Update : 2024-05-07 Size : 1589248 Publisher : Robert
【VHDL-FPGA-Verilog】 FSM_Moore DL : 0: altera Quartus II FSM使用可設定時間波形，手動調整波形頻率。 (含電路) -altera Quartus II FSM can be set using the time waveform, manually adjust the frequency waveform. (With circuit)
Update : 2024-05-07 Size : 114688 Publisher : 陳小龍
【VHDL-FPGA-Verilog】 new_pwm DL : 0: 一个PWM参数器，里面有所有仿真结果，在QUARTUS软件打开，自己设计的-A PWM parameters, and there are all the simulation results, in the Quartus software to open, own design
Update : 2024-05-07 Size : 231424 Publisher : 杨杨
【VHDL-FPGA-Verilog】 zzs4 DL : 0: 用verilog实现的电子日历程序,在Quartus II上编译通过并成功实现-Using Verilog to achieve the electronic calendar program, compiled in the Quartus II and successfully achieved through
Update : 2024-05-07 Size : 662528 Publisher : 张兵
【VHDL-FPGA-Verilog】 jishiqi DL : 0: 用verilog实现的记时器程序,在Quartus II上编译通过并成功运行-Realized by Verilog program in mind when, in the Quartus II compiled and successfully run through
Update : 2024-05-07 Size : 2221056 Publisher :
【VHDL-FPGA-Verilog】 shuzhijietiaoqu DL : 0: 基于FPGA的全数字调制解调器设计实例，包含有Matlab程序和Quartus程序-FPGA-based all-digital modem design example, contains the procedures and Quartus program Matlab
Update : 2024-05-07 Size : 656384 Publisher :
【Communication-Mobile】 Quartuspn DL : 0: 伪随机图案发生器的Quartus源程序，CDMA通信的学习中用硬件语言实现伪随机码。-Pseudo-random pattern generator Quartus source, CDMA communications hardware used to study the language to achieve pseudo-random code.
Update : 2024-05-07 Size : 4096 Publisher : w
【Other】 quartus2 DL : 0: 跟随本手册学习 Quartus II 软件，了解此软件如何帮助您提高效率并缩短设计周期，如何与现有可编程逻辑设计流程集成以及如何快速有效地达到设计、性能和时间要求。-Follow the manual to learn Quartus II software, to understand this software can help you increase efficiency and shorten the design cycle, how to with the existing programmable logic design process integration and how to quickly and efficiently to meet the design, performance and time requirements.
Update : 2024-05-07 Size : 3089408 Publisher : eroad
【Other】 quartusii_handbook DL : 0: quartus ii 使用手册希望大家喜欢！-Manual quartus ii hope you like!
Update : 2024-05-07 Size : 18276352 Publisher : falcon

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