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【Other Embeded program】 SVGA_quartus DL : 0: 在开发板上实现svga条形信号发生器的源代码，是在quartus II 6.0的开发环境中运行的-achieved in the development of board svga strip signal generator source code, in quartus II 6.0 development environment running on
Update : 2024-05-06 Size : 215040 Publisher : 孙彤
【VHDL-FPGA-Verilog】 656to601 DL : 0: 本程序实现视频图象的CCIR656转换CCIR601格式,使用的环境是Quartus II 4.0-the program CCIR656 video image conversion CCIR601 format, The environment is the use of Quartus II 4.0
Update : 2024-05-06 Size : 564224 Publisher : 吉克
【VHDL-FPGA-Verilog】 lcd4quartus DL : 0: 128×64单色点阵LCD的quartus工程文件-128 x 64 monochrome dot-matrix LCD quartus works documents
Update : 2024-05-06 Size : 703488 Publisher : HYP
【Crack Hack】 3des-VHDL DL : 0: 3des的VHDL实现，适用于quartus环境-3des VHDL applicable to the environment quartus
Update : 2024-05-06 Size : 95232 Publisher : xin
【Other】 AlteraQuartusII6.0crack DL : 0: Altera Quartus II 6.0 破解文件-Altera Quartus II 6.0 crack documents
Update : 2024-05-06 Size : 6144 Publisher : 王国华
【VHDL-FPGA-Verilog】 2FSK2psk DL : 0: ２ＦＳＫ２ＰＳＫ－二进制频移键控和相移键控信号发生器的源程序，是基于ＱＵＡＲＴＵＳ　ＩＩ软件平台，使用ＶＨＤＬ语言-2FSK2PSK-binary frequency shift keying and phase shift keying signal generator source, QUARTUS II is based on the software platform, the use of VHDL
Update : 2024-05-06 Size : 1024 Publisher : 张全文
【Other】 q2_7_license DL : 0: altera quartus 2 7.0 许可文件-altera quartus 2 7.0 permit documents
Update : 2024-05-06 Size : 6144 Publisher : 尤
【VHDL-FPGA-Verilog】 suij DL : 0: 硬件编程实现伪随机交织器和随机交织器，应用环境Quartus II5.0-hardware programming pseudo-random interleaver and random interleaver, application environment Quartus II5.0
Update : 2024-05-06 Size : 2048 Publisher : 孟旭
【Documents】 QuartusII_sum DL : 0: Altera Quartus II使用方法的总结性文件-Altera Quartus II use of the concluding document
Update : 2024-05-06 Size : 294912 Publisher : 光辉
【Embeded-SCM Develop】 quartusGuide DL : 0: 设计输入 ! 多种设计输入方法 – Quartus II • 原理图式图形设计输入 • 文本编辑 – AHDL, VHDL, Verilog • 内存编辑 – Hex, Mif – 第三方工具 • EDIF • HDL • VQM – 或采用一些别的方法去优化和提高输入的灵活性: • 混合设计格式 • 利用LPM和宏功能模块来加速设计输入-design input! Design a variety of input methods-Quartus
Update : 2024-05-06 Size : 844800 Publisher : fgghh
【VHDL-FPGA-Verilog】 Quartus_vhdl DL : 0: 用QUARTUS编译通过的等精度频率计，我错误，但有几个警告（不影响设计）。我的毕业设计啊！！！ -QUARTUS used by the compiler, and other precision frequency, I am wrong. But there are several warning (not affect design). I graduated from the design ah! ! !
Update : 2024-05-06 Size : 44032 Publisher : 刘刚
【VHDL-FPGA-Verilog】 b8bit_adder DL : 0: 8位的加法器设计，分4个工程完成的，用的是Quartus II软件。-eight of the adder design, four hours to complete the project, using the Quartus II software.
Update : 2024-05-06 Size : 520192 Publisher : jk
【VHDL-FPGA-Verilog】 shuzilvboqideyingjianshixian DL : 0: 数字滤波器的硬件实现，里面实例可以直接在quartus中运行-Digital Filter hardware, which can be directly examples run in quartus
Update : 2024-05-06 Size : 3072 Publisher : sunny_girl
【VHDL-FPGA-Verilog】 IIS_VHDL DL : 0: VHDL实现了IIS接口程序，在Quartus II 6.0上编译通过，在板子上可以读取IIS数据-IIS VHDL interface procedures, the Quartus II 6.0 compiled by the board can read data IIS
Update : 2024-05-06 Size : 962560 Publisher : 小刚
【VHDL-FPGA-Verilog】 GuangShanChi DL : 0: 光栅尺的四细分和辩向电路，并具有计数器功能，利用Quartus综合，可以参考-Grating four segments and the dialectic to the circuit, and have counter functions, using Quartus integrated, can refer to
Update : 2024-05-06 Size : 694272 Publisher : 蔡有才
【VHDL-FPGA-Verilog】 leon3-altera-ep2s60-ddr DL : 0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Update : 2024-05-06 Size : 114688 Publisher :
【Other】 SignalTapII DL : 0: Altera公司Quartus II软件的逻辑分析使用流程，中文版本。该文件详细说明了使用SingalTapII的流程和基本使用方法，对使用FPGA的人有很大帮助。
Update : 2024-05-06 Size : 1125376 Publisher : 邓奕堃
【VHDL-FPGA-Verilog】 srbjq DL : 0: quartus环境下开发的三人表决器（三种不同的描述方式）maxplusII兼容
Update : 2024-05-06 Size : 1024 Publisher :
【Documents】 intro_to_quartus2_chinese DL : 0: 本手册针对的读者是 Quartus II 软件的初学者，它概述了可编程逻辑设计中 Quartus II 软件的功能。
Update : 2024-05-06 Size : 3912704 Publisher : 孙强
【ELanguage】 Crack_QII71_b156 DL : 0: Quartus v7.1的key_gen b156破解器-The Quartus v7.1 crack key_gen b156 browser
Update : 2024-05-06 Size : 6144 Publisher : jacky

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