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【VHDL-FPGA-Verilog】 core_arm.tar DL : 0: ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Update : 2024-05-07 Size : 666624 Publisher : 周华茂
【VHDL-FPGA-Verilog】 vhdl_crc DL : 0: 在quartus中用VHDL语言开发的crc校验-Quartus VHDL language used in the development of CRC Checksum
Update : 2024-05-07 Size : 163840 Publisher : 夏杰
【Software Engineering】 mycpu DL : 0: Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。-Quartus II 5.0 written under a single bus architecture of the CPU design, including controllers, computing devices, such as decoding circuitry. Simulated clock pulse is also given. Has been run through the Quartus II 5.0. Can be addressed to the need to design bus architecture students CPU reference point.
Update : 2024-05-07 Size : 800768 Publisher : 陈佳
【MiddleWare】 MIF_create DL : 0: MIF文件生成器用于quartus II等软件的ROM表mif文件生成-MIF file generator quartus II software for the ROM table to generate mif file
Update : 2024-05-07 Size : 221184 Publisher : 高
【Embeded-SCM Develop】 i2c_IP DL : 0: altera 的i2c ip核，可直接调用在quartus中把库指向文件位置就可-altera the i2c ip nuclear, can be directly called in the Quartus point in the database file location can be
Update : 2024-05-07 Size : 7168 Publisher : 李涛
【Other】 uart_IP DL : 0: altera 的uart ip核，可直接调用在quartus中把库指向文件位置就可-altera the uart ip nuclear, can be directly called in the Quartus point in the database file location can be
Update : 2024-05-07 Size : 5120 Publisher : 李涛
【VHDL-FPGA-Verilog】 miaobiao DL : 0: 完整的的倒计时秒表设计（指示带闪烁）ＶＨＤＬ代码，Ｑuartus 2开发环境，Archive文件，在Ｑuartus2解压即可。-Complete countdown stopwatch design (with flashing instructions) VHDL code, Quartus 2 development environment, Archive documents, in Quartus2 can extract.
Update : 2024-05-07 Size : 113664 Publisher : 李淡
【VHDL-FPGA-Verilog】 quartus6.0 DL : 0: Atlera 公司的开发软件平台quartus 6.0的license-Atlera company quartus 6.0 to develop the software platform of the license
Update : 2024-05-07 Size : 2048 Publisher : guobo
【VC/MFC】 quartus DL : 0: 此为quautus教程,请各位仔细去看吧,有不懂的和我联系-This is quautus tutorial, please look at it carefully, and I do not have contact
Update : 2024-05-07 Size : 847872 Publisher : luoai
【VHDL-FPGA-Verilog】 eeprom DL : 0: eeprom的Verilog HDL源代码，含eeprom的读写！Quartus II5.0平台测试通过！-EEPROM of the Verilog HDL source code, including reading and writing EEPROM! Quartus II5.0 platform test!
Update : 2024-05-07 Size : 521216 Publisher :
【VHDL-FPGA-Verilog】 quartusII DL : 0: 华为内部教程(比较早的) 对Quartus 流程中各阶段进行较为详细的介绍最后简要介绍了一下如何使用TCL进行Quartus 流程的脚本方式运行-Huawei internal Tutorial (relatively early) on the flow in the various stages of Quartus conduct a more detailed introduction Finally then briefly introduce how to use the TCL flow for Quartus script run
Update : 2024-05-07 Size : 2477056 Publisher : 付茗
【VHDL-FPGA-Verilog】 FT245_R_W DL : 0: USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.
Update : 2024-05-07 Size : 1644544 Publisher :
【Software Engineering】 modelsim DL : 0: 这一资料详细讲解了如何在quartus中使用modelsim，具有一定的参考价值-This information is detailed account of how to use Quartus modelsim, has a certain reference value
Update : 2024-05-07 Size : 160768 Publisher : weiwei
【VHDL-FPGA-Verilog】 shuzixitongshiyan DL : 0: 这个给QuartusII初学者用的，里面很清楚的通过几个例子来告诉怎么运用QuartusII．实验1：Quartus入门实验2：简单的组合逻辑电路设计实验3：七段数码管显示实验4：BCD码显示及运实验5：触发器和计数器实验6：存储器的设计实验7：基于DE2 的SOPC系统开发附录：-This QuartusII beginners to use, which is very clear through several examples to tell how the use of QuartusII. Experiment 1: Quartus entry Experiment 2: a simple combinational logic circuit design of experiment 3: Seven-Segment LED display experiment 4: BCD code display and shipped experiment 5: flip-flops and counters experiment 6: the design of memory test 7: Based on DE2 the SOPC System Development Appendix:
Update : 2024-05-07 Size : 754688 Publisher : yulieyar
【VHDL-FPGA-Verilog】 judgedisplay DL : 0: FPGA驱动数码管，本人编写的vhdl源程序，QUARTUS II调试成功-FPGA-driven digital tube, I prepared VHDL source code, QUARTUS II debugging success
Update : 2024-05-07 Size : 1024 Publisher : 王真
【Other Embeded program】 VBuffer.1.1 DL : 0: 视频采集，存储，发送的VERILOG源程序； QUARTUS II 6.0调试通过。-Video capture, store, send the Verilog source code QUARTUS II 6.0 debug through.
Update : 2024-05-07 Size : 4146176 Publisher : yan
【VHDL-FPGA-Verilog】 thefirstexampleforQuartuslearners DL : 0: 一个完整的QUARTUS设计例子，初学QUARTUS的人必看！-Quartus a complete design example, a person must-see Quartus beginner!
Update : 2024-05-07 Size : 1943552 Publisher : 钱能
【VHDL-FPGA-Verilog】 CC DL : 0: quartus 的一个实例,希望对刚刚学习quartus 的人有点帮助-Quartus an example, in the hope that people just learning a little help Quartus
Update : 2024-05-07 Size : 1039360 Publisher : 甘同同
【Embeded-SCM Develop】 429_enc_dec DL : 1: Quartus开发环境下开发的Arinc 429总线收发器工程，由于产权问题，提供的程序有删减，标号未尽规范。-Quartus development environment developed under the Arinc 429 bus transceiver works, because the issue of property rights, provided procedures are deleted, not standardized labeling.
Update : 2024-05-07 Size : 679936 Publisher : wangyunshann
【VHDL-FPGA-Verilog】 uart DL : 0: VHDL编写的异步通信串行口设计用Quartus工具编译-VHDL prepared the design of serial asynchronous communication tool used Quartus compiler
Update : 2024-05-07 Size : 212992 Publisher : 朱兆斌

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