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【VHDL-FPGA-Verilog】 VHDL-Clock DL : 0: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Update : 2024-05-07 Size : 4096 Publisher : 单单
【VHDL-FPGA-Verilog】 ref-ualaw DL : 0: A率/u率压缩与解压缩的IP核，。 # 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。-A rate/u rate compression and decompression of the IP core,. By AHDL# languages, and the Quartus II MaxplusII use, the source code encryption.
Update : 2024-05-07 Size : 119808 Publisher : zhangkun
【Other】 QuartusIIintroduction DL : 0: Quartus II 简介，对熟悉和学习Quartus II 很有帮助，全部为中文翻译。-Quartus II profiles, and learn familiar with the Quartus II helpful, All of the Chinese translation.
Update : 2024-05-07 Size : 3101696 Publisher : 曾
【Software Engineering】 quartus_Chinese_Introduction DL : 0: quartus 软件应用中文教程，包含一些高级的用法等。-quartus Chinese Directory software applications, including some senior usage, and so on.
Update : 2024-05-07 Size : 6616064 Publisher : Frank
【Software Engineering】 intro_to_quartus2_v6.0_chinese DL : 0: quartus II 6.0 中文使用手册 intro_to_quartus2_chinese-Chinese quartus II 6.0 manual intro_to_quartus2_ english
Update : 2024-05-07 Size : 2068480 Publisher : yysh
【VHDL-FPGA-Verilog】 seq_gen_576 DL : 0: 高清电视HDTV信号发生器，576P逐行，VHDL语言，ALTERA的Quartus II开发平台-HDTV HDTV signal generator, 576P progressive, VHDL, Altera's Quartus II development platform
Update : 2024-05-07 Size : 161792 Publisher : lidan
【Other】 counter60 DL : 0: 这是我们做的一个作业摸60计数器，用Quartus ii 做的，内容齐全不可不看。-This is the one we do feel 60 counter operation with Quartus ii do. complete contents can not see.
Update : 2024-05-07 Size : 138240 Publisher : qqq
【Special Effects】 videofram DL : 0: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
Update : 2024-05-07 Size : 1024 Publisher : 陈刚峰
【Other】 Designing_with_Quartus DL : 0: 1)Learn more about the capabilities in Quartus: 2)Learn to use different design entry techniques 2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor, Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic -1) Learn more about the capabilities in Qua rtus : 2) Learn to use different design entry techniqu es 2) Design entry methods available within Qua rtus Text editor, Block diagram/schematic file editor, Quartus interface with design entry/synthesi s tools from Exemplar, Synopsys. Synplicity and Viewlogic
Update : 2024-05-07 Size : 2713600 Publisher : Jawen
【VHDL-FPGA-Verilog】 altera_lcd_controller DL : 0: quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
Update : 2024-05-07 Size : 26624 Publisher : 张建
【VHDL-FPGA-Verilog】 VHDL_Memory_Library_Code DL : 0: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Update : 2024-05-07 Size : 23552 Publisher : Jawen
【ARM-PowerPC-ColdFire-MIPS】 CrackQII60 DL : 0: quartus6.0+nios2 6.0的License,将hostid改为你自己的网卡号即可使用quartus和nios6.0的全部功能-quartus6.0 nios2 6.0 License, hostid to read your own card can be used quartus, and the full functionality of nios6.0
Update : 2024-05-07 Size : 5120 Publisher : hrui
【source in ebook】 Crack_QII60_b178 DL : 0: Quartus II 6.0完全Crack文件-Quartus II 6.0 document completely Crack
Update : 2024-05-07 Size : 6144 Publisher : 江纵海
【VHDL-FPGA-Verilog】 23565785scan_led DL : 0: Quartus环境下的7段扫描显示电路的源程序-Quartus environment of the seven scanning display circuit of the source
Update : 2024-05-07 Size : 128000 Publisher : 吴语
【VHDL-FPGA-Verilog】 234352325DECL7S DL : 0: Quartus环境下的7段译码管的扫描显示电路-Quartus environment of the seven decoding of the scan show circuit
Update : 2024-05-07 Size : 111616 Publisher : 吴语
【Embeded-SCM Develop】 ddsquartus DL : 0: 使用QUARTUS 2编译的DDS的源码-QUARTUS use two compiled the DDS source
Update : 2024-05-07 Size : 533504 Publisher : 吴
【Software Engineering】 verilog50% DL : 0: 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the simulation results. Design used EPM7064AETC44-7 CPLD. In QUARTUS II 4.2 software platform.
Update : 2024-05-07 Size : 187392 Publisher : li
【Other】 SOPC11 DL : 0: 潘松老师写的一本关于sopc实用教程的图书，包括quartus的使用，基于dspbuilder＆matlab的现代dsp设计以及nios嵌入式系统开发等内容，非常不错的一本图书。-Pan Song written by a teacher on the SOPC Practical Guide books, including the use of Quartus, based on the dspbuilder
Update : 2024-05-07 Size : 38735872 Publisher : 可难
【Embeded-SCM Develop】 nios_uart DL : 0: 基于Nios II的串口通信，在quartus的开发环境中进行的实验-based Nios II Serial Communication in quartus development environment for the conduct of the experiment
Update : 2024-05-07 Size : 9630720 Publisher : 孙彤
【Other Embeded program】 38encode DL : 0: 三八译码器的源代码，在quartus II 6.0中进行进行设计的，有vhdl源代码-March 8 decoder source code, in quartus II 6.0 for the design, Source code is vhdl
Update : 2024-05-07 Size : 151552 Publisher : 孙彤

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