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【Other】 QuartusIIstudy DL : 0: quartus II的入门与提高。进一步深入介绍该软件的使用。-quartus II and raise the entry. Further introduced the use of the software.
Update : 2024-05-19 Size : 3098624 Publisher : a_zhuo
【VHDL-FPGA-Verilog】 Quartus_II_called_ModelSim_simulation DL : 0: BJ-EPM240V2实验例程以及说明文档实验之十五Quartus II调用ModelSim仿真实例-BJ-EPM240V2 experimental test routines as well as documentation of the Quartus II 15 ModelSim simulation calls
Update : 2024-05-19 Size : 421888 Publisher : 王建毅
【VHDL-FPGA-Verilog】 NIOS_TFT DL : 0: 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
Update : 2024-05-19 Size : 14394368 Publisher : 涂龙
【VHDL-FPGA-Verilog】 clk DL : 0: Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules.
Update : 2024-05-19 Size : 512000 Publisher : kg21kg
【VHDL-FPGA-Verilog】 CLK_V DL : 0: Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用Verilog语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. The use of Verilog language.
Update : 2024-05-19 Size : 598016 Publisher : kg21kg
【VHDL-FPGA-Verilog】 clk_vhdl DL : 0: Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
Update : 2024-05-19 Size : 652288 Publisher : kg21kg
【VHDL-FPGA-Verilog】 stopwatch DL : 0: Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
Update : 2024-05-19 Size : 464896 Publisher : kg21kg
【VHDL-FPGA-Verilog】 JIJIAQI DL : 0: Quartus II工程压缩文件，是一个典型的基于FPGA的计价器工程项目，有有限状态机、50MHz分频、计数、译码、动态扫描等模块。-Quartus II project files, is a typical FPGA-based project of the meter, there are finite state machine, 50MHz frequency, counting, decoding, dynamic scanning module.
Update : 2024-05-19 Size : 795648 Publisher : kg21kg
【VHDL-FPGA-Verilog】 servo_module_worked DL : 0: verilog pwm to control servo motor on quartus
Update : 2024-05-19 Size : 21504 Publisher : frankie
【VHDL-FPGA-Verilog】 PWM DL : 0: verilog pwm to control servo motor on quartus, with microprocessor generated from sopc and connected with sram-verilog pwm to control servo motor on quartus
Update : 2024-05-19 Size : 21504 Publisher : frankiecoco
【VHDL-FPGA-Verilog】 pwm DL : 0: verilog实现PWM 开发环境 QUARTUS II7.0-verilog to achieve PWM development environment QUARTUS II7.0
Update : 2024-05-19 Size : 54272 Publisher : exun
【VHDL-FPGA-Verilog】 QUARTUSIIIntroduce DL : 0: 本手册针对的读者是 Quartus II 软件的初学者，它概述了可编程逻辑设计中 Quartus II 软件的功能-This manual is aimed at readers of the Quartus II software for beginners, it provides an overview of programmable logic in the Quartus II design software
Update : 2024-05-19 Size : 3096576 Publisher : 光辉
【VHDL-FPGA-Verilog】 usb-blaster DL : 0: quartus多种USB-bletera 自制下载线！
Update : 2024-05-19 Size : 2328576 Publisher : 陈长佳
【VHDL-FPGA-Verilog】 The-Duck DL : 0: Crack for Quartus II 8.0
Update : 2024-05-19 Size : 764928 Publisher : FPGABug
【DSP program】 TaxiPriceCounter DL : 0: 数字逻辑实验作品，在maxplus2下开发的出租车计价器系统（Quartus也可运行），实现基本计价功能，可以设置单价（实验报告中友设置方法），内含实验报告，直接打开taxi_price_counter_final.gdf即可运行-Digital logic experiment works, developed in maxplus2 Taximeter system (Quartus can also be run), the realization of the basic pricing function, can set the unit price (the report of the Friends of the experimental set methods), including experimental reports, that is directly open taxi_price_counter_final.gdf run
Update : 2024-05-19 Size : 4012032 Publisher : 昕明儿
【VHDL-FPGA-Verilog】 crack_qii90 DL : 0: altera quartus 9 crack working
Update : 2024-05-19 Size : 14336 Publisher : sreejith s
【VHDL-FPGA-Verilog】 quartus DL : 0: quartus中常见错误的解析以及解决办法，主要是VHDL也verilog HDL-Common Errors in quartus and the analytic solutions is mainly VHDL also verilog HDL
Update : 2024-05-19 Size : 6144 Publisher : 彭文彬
【VHDL-FPGA-Verilog】 1 DL : 0: 硬件编程设计,Quartus程序的源码,注释详细,是你学校FPGA/QuartusII的好代码!-Programming hardware, Quartus source process, comments in detail, is your school FPGA/QuartusII good code!
Update : 2024-05-19 Size : 6847488 Publisher : 南才北往
【VHDL-FPGA-Verilog】 lpm_ram DL : 0: 一个基于quartus的LPM_RAM例子，VHDL语言写的，通过仿真测试-Quartus the LPM_RAM based on examples, VHDL language, and through simulation testing
Update : 2024-05-19 Size : 221184 Publisher : a64577122
【VHDL-FPGA-Verilog】 DE2_NET DL : 0: 用DE2开发板实现的网络控制器。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。程序已经过测试，功能完好。-DE2 development board with the realization of the network controller. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in Nios2. Procedure has been tested, function well.
Update : 2024-05-19 Size : 1601536 Publisher : 符玉襄

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