Search - ddr

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【Other resource】 ref-ddr-sdram-vhdl DL : 0: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Update : 2008-10-13 Size : 1031656 Publisher : 包盛花
【Other】 ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2008-10-13 Size : 437055 Publisher : kevin
【Other resource】 ddr DL : 0: ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
Update : 2008-10-13 Size : 1023228 Publisher : yuling
【Other resource】 leon3-altera-ep2s60-ddr DL : 0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Update : 2008-10-13 Size : 114780 Publisher : king.xia
【Other resource】 cpu-leon3-altera-ep2s60-ddr DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！
Update : 2008-10-13 Size : 753022 Publisher : zhao onely
【Other resource】 ddr DL : 0: davincievm 6446 記憶體DDR撿測
Update : 2008-10-13 Size : 37365 Publisher : 謝震威
【VHDL-FPGA-Verilog】 ddr DL : 0: ddr控制器
Update : 2010-10-13 Size : 473884 Publisher : huangqiangryan@sina.com
【Other Embeded program】 DDR SDRAM控制器的VHDL代码已经测试 DL : 0: DDR SDRAM控制器的VHDL代码已经测试
Update : 2011-02-08 Size : 15466 Publisher : bbk2000
【Program doc】 cyclone_ug_ddr_sdram DL : 0: ddr——sdram
Update : 2011-03-14 Size : 1005118 Publisher : xiaoxiong146480
【Other Embeded program】 DDR内存接口VC源程序IP核 DL : 0: 很难看到的 DDR内存接口VC源程序IP核！各大公司用它卖钱的哦！
Update : 2012-04-06 Size : 752193 Publisher : vq2275
【Embeded-SCM Develop】 ref-ddr-sdram-verilog DL : 0: sdram的verilog的源码实现-sdram verilog source code realizes
Update : 2024-05-03 Size : 904192 Publisher : zfhustb
【File Operate】我的SDRAM资料收藏 DL : 0: RAM（Random Access Memory）随机存取存储器对于系统性能的影响是每个PC用户都非常清楚的，所以很多朋友趁着现在的内存价格很低纷纷扩容了内存，希望借此来得到更高的性能。不过现在市场是多种内存类型并存的，SDRAM、DDR SDRAM、RDRAM等等，如果你使用的还是非常古老的系统，可能还需要EDO DRAM、FP DRAM（块页）等现在不是很常见的内存-RAM (Random Access Memory) random access memory system performance for the impact of each PC users are very clear, so many of my friends now take advantage of the low prices have memory expansion memory, with a view to get higher performance. But now the market is a mixture of both types of memory, SDRAM, DDR SDRAM, RDRAM, etc. If you use or the very old, may also need to EDO DRAM, FP DRAM (block pages) is now is not very common memory
Update : 2024-05-03 Size : 775168 Publisher : 周卫成
【File Operate】完全硬件手册 DL : 0: RAM（Random Access Memory）随机存取存储器对于系统性能的影响是每个PC用户都非常清楚的，所以很多朋友趁着现在的内存价格很低纷纷扩容了内存，希望借此来得到更高的性能。不过现在市场是多种内存类型并存的，SDRAM、DDR SDRAM、RDRAM等等，如果你使用的还是非常古老的系统，可能还需要EDO DRAM、FP DRAM（块页）等现在不是很常见的内存-RAM (Random Access Memory) random access memory system performance for the impact of each PC users are very clear, so many of my friends now take advantage of the low prices have memory expansion memory, with a view to get higher performance. But now the market is a mixture of both types of memory, SDRAM, DDR SDRAM, RDRAM, etc. If you use or the very old, may also need to EDO DRAM, FP DRAM (block pages) is now is not very common memory
Update : 2024-05-03 Size : 1052672 Publisher : 周卫成
【VHDL-FPGA-Verilog】 ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2024-05-03 Size : 776192 Publisher : 张涛
【VHDL-FPGA-Verilog】 ddr_verilog_xilinx DL : 0: DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
Update : 2024-05-03 Size : 131072 Publisher : 陈旭
【VHDL-FPGA-Verilog】 ddr DL : 0: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Update : 2024-05-03 Size : 2048 Publisher : 孙强
【VHDL-FPGA-Verilog】 FPGA-DDR-SDRA DL : 0: 基于FPGA 的DDR SDRAM高速数据采集的应用-DDR SDRAM high-speed FPGA-based data acquisition applications
Update : 2024-05-03 Size : 309248 Publisher : 周勇
【VHDL-FPGA-Verilog】 ddr DL : 0: 基于FPGA的ddr控制器的设计与实现，verilog，ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
Update : 2024-05-03 Size : 179200 Publisher : 洪依
【VHDL-FPGA-Verilog】 DDR-SDRAM_IP_core DL : 0: DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Update : 2024-05-03 Size : 474112 Publisher : zyy
【DSP program】 ddr DL : 0: DM36x平台下的DDR测试程序（c源码），包括对DDR的写入和读出。(The DDR test program (c source code) under the DM36x platform, including the writing and reading of the DDR.)
Update : 2024-05-03 Size : 40960 Publisher : 一夏

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