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【Other】 ddr_ctrlv DL : 0: ddr ram controller vhdl code
Update : 2024-05-03 Size : 55296 Publisher : heyong
【Windows Develop】 ddr_sdr_V1_0 DL : 0: 关于DDR控制器方面的，可以看看，里面有较完整的代码和说明。-On the DDR controllers, you can see, there are more complete code and description.
Update : 2024-05-03 Size : 38912 Publisher : yuhl
【VHDL-FPGA-Verilog】 rtl DL : 0: DDR控制器已通过FPGA 验证大家不要错过哦-DDR controller has passed FPGA to verify that we will not miss Oh
Update : 2024-05-03 Size : 52224 Publisher : kin
【DSP program】 ddr2 DL : 0: TI dm643 DDR 配置源代码,可以直接下载到板子上运行-TI dm643 DDR configuration source code, can be directly downloaded to the board to run
Update : 2024-05-03 Size : 5120 Publisher : 张健
【Technology Management】 W949D2BBAP01001W DL : 0: 华邦W949D2BBAP01001W ddr芯片spec。网上找不到的。-W949D2BBAP01001W ddr Winbond chip spec. Internet can not be found.
Update : 2024-05-03 Size : 823296 Publisher : 徐钧
【Communication-Mobile】 SmallCore_SDRAM DL : 0: MagicSopc DDR-Sdram
Update : 2024-05-03 Size : 576512 Publisher : Rainy
【SCM】 DDR_SDRAM_DesignSummarize DL : 0: 基于Xilinx Spartan系列开发板的DDR SDRAM设计方案及经验总结!-Based on the Xilinx Spartan family of development boards and the DDR SDRAM design experience!
Update : 2024-05-03 Size : 338944 Publisher : 曾娟丽
【Other】 128Mb_ddr DL : 0: 128Mb DDR verilog源程序-128Mb DDR verilog source code
Update : 2024-05-03 Size : 23552 Publisher : tiantian
【VHDL-FPGA-Verilog】 Xil3S500E_Serial_Flash_v81 DL : 0: 这是一个利用xilinx的macroblaze将用户程序由flash读取至ddr内存的例程，关键是bootloader的写法。-This is a use of Xilinx macroblaze the user program will read from flash memory to ddr routine, the key is the wording of bootloader.
Update : 2024-05-03 Size : 1334272 Publisher : weichengguanzhe
【VHDL-FPGA-Verilog】 DDR_SDRAM_verilog DL : 0: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
Update : 2024-05-03 Size : 752640 Publisher : 宋珂
【Software Engineering】 mx27ads_x33 DL : 0: i.mx27开发板的整套详细原理图，包括：DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST,FEC PHY, UART,JTAG等等接口-i.MX27 development board schematic details of the package, including: DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST, FEC PHY, UART, JTAG interface, etc.
Update : 2024-05-03 Size : 741376 Publisher : 清木
【VHDL-FPGA-Verilog】 DDR_SDRAM_controller DL : 0: ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
Update : 2024-05-03 Size : 1021952 Publisher : shroy
【VHDL-FPGA-Verilog】 DDR_SDRAM_controller DL : 0: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Update : 2024-05-03 Size : 132096 Publisher : xbl
【Other】 DDR_allegro DL : 0: 用allegro画的ddr存储器电路。六层板设计，很好的参考资料-Allegro painting with ddr memory circuit. Six-storey plate design, very good reference
Update : 2024-05-03 Size : 372736 Publisher : 朱宝军
【Software Engineering】 20060510191318991 DL : 0: ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
Update : 2024-05-03 Size : 2253824 Publisher : 盛雪飞
【Linux-Unix】 Hardware_Test_Programs DL : 0: ccs下对dm6446的测试程序，能够检测ddr,nandflash,uart,usb等硬件电路的裸板测试代码，包含库文件，板级gel文件，开发环境在TI ccs3.3下。-ccs on DM6446 testing procedures can detect ddr, nandflash, uart, usb hardware such as the bare circuit board to test the code, including library files, board-level gel documentation, development environment in the next TI ccs3.3.
Update : 2024-05-03 Size : 3568640 Publisher : 王枫
【VHDL-FPGA-Verilog】 DDR_SDRAM DL : 0: 利用fpga读写ddr的源代码实测可以使用-Ddr use FPGA to read and write the source code can use the measured
Update : 2024-05-03 Size : 474112 Publisher : 朱宝军
【VHDL-FPGA-Verilog】 DDR DL : 0: leon ep2s60 ddr use altera statix2 and add ddr sdram-leon ep2s60 ddr
Update : 2024-05-03 Size : 752640 Publisher : free
【Software Engineering】 K4H511638脰D DL : 0: Data Sheet 512Mb D-die DDR SDRAM Specification
Update : 2024-05-03 Size : 292864 Publisher : Naeem
【Other】 testbench DL : 0: ddr sdram controller datd module source code
Update : 2024-05-03 Size : 3072 Publisher : KrishnaKishore

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