Search - ddr

Search - ddr - List

【Software Engineering】 ddr_sdr_V1_1 DL : 0: its the vhdl stuff for ddr sdram controller nice one easily understandable-its the vhdl stuff for ddr sdram controller nice one easily understandable
Update : 2024-05-03 Size : 37888 Publisher : james
【VHDL-FPGA-Verilog】 sdram_controller_latest.tar DL : 0: sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.
Update : 2024-05-03 Size : 30720 Publisher : Andrei
【SCM】 S3C6410_core_sch DL : 0: ok6410最新核心板最小系统原理图，包含mobile ddr， nandflash-ok6410 latest minimum system schematic core board, including mobile ddr, nandflash
Update : 2024-05-03 Size : 128000 Publisher : jerry
【Other Embeded program】 Hardware_and_Layout_Design_Considerations_for_DDR_ DL : 0: DDR SDRAM接口的硬件和布线设计指南。DDR SDRAM的传输速度越来越高，对走线的要求也越来越高。-DDR SDRAM HARDWARE LAYOUT DESIGN
Update : 2024-05-03 Size : 692224 Publisher : 朱伟华
【VHDL-FPGA-Verilog】 DDR_SDRAM_design_and_conclusion DL : 0: DDR SDRAM总结文档，描述了DDR IP的设计挑战，接口时序，模块设计原则，调试技巧及应用指南-DDR SDRAM summary document describing the design challenge of DDR IP, interface timing, modular design principles, debugging skills and Application Guide
Update : 2024-05-03 Size : 338944 Publisher : 李中梅
【VHDL-FPGA-Verilog】 DDR_SDRAM DL : 0: ddr sdram 的控制程序，lattice的，比较好用的，大家-ddr sdram control program, lattice, and relatively easy to use, and we look
Update : 2024-05-03 Size : 8483840 Publisher : 熊熊
【VHDL-FPGA-Verilog】 Altera_DDR_controller_core DL : 0: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Update : 2024-05-03 Size : 752640 Publisher : 沈志
【VHDL-FPGA-Verilog】 DDRSDRAMconclude DL : 0: DDR SDRAM技术总结介绍DDR SDRAM的一些概念和难点着重讲解主流DDRII的技术最后结合硬件设计提出一些参考 -DDR SDRAM DDR SDRAM Technical Summary describes some of the concepts and difficult to explain the mainstream DDRII technology focused on the final hardware design combined with some reference
Update : 2024-05-03 Size : 2262016 Publisher : 董萌
【VHDL-FPGA-Verilog】 XAPP200_ddr_sdram_64b DL : 0: Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix
Update : 2024-05-03 Size : 1626112 Publisher : jc
【VHDL-FPGA-Verilog】 DDRSDRAM_controller DL : 0: ddr sdram控制器，lattice器件的参考设计，比较详细-ddr sdram controller, lattice components of the reference design, very detailed
Update : 2024-05-03 Size : 693248 Publisher :
【Other】 ddr DL : 0: DDR solution for problem in NPC contest
Update : 2024-05-03 Size : 1024 Publisher : GestureWorld
【VHDL-FPGA-Verilog】 ddr_100Mhz_2011.03.12 DL : 0: 这个工程是用xilinx的MIG生成的对于spartan 3E的实验板的ddr的控制器，我已经能够在上面修改之后加入自己的思想，包括两个dcm的模块。-This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding his own ideas, including the two dcm module.
Update : 2024-05-03 Size : 6132736 Publisher : 张元甲
【Linux-Unix】 DDR-failure-analysis DL : 0: DDR failure analysis
Update : 2024-05-03 Size : 800768 Publisher : leego
【VHDL-FPGA-Verilog】 DDR-SDRAM DL : 0: 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集，并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to achieve use of technology to achieve direct data acquisition, and automatic calibration circuit to adjust the data in line delay.
Update : 2024-05-03 Size : 54272 Publisher : syf
【VHDL-FPGA-Verilog】 DDR DL : 0: 关于DDR布线规范，用于指导PCB布线.-Wiring on the DDR specification, PCB layout for
Update : 2024-05-03 Size : 1957888 Publisher : tl
【VHDL-FPGA-Verilog】 emb-dev-c3-appsel DL : 0: vhdl code for altera ddr design
Update : 2024-05-03 Size : 4072448 Publisher : clement
【VHDL-FPGA-Verilog】 TEST-BENCH.vhd DL : 0: test bench for ddr 1
Update : 2024-05-03 Size : 2048 Publisher : shiva
【DSP program】 tests DL : 0: 6437开发板测试程序,RAM,DDR,LED,RTC,USB,VIDEO,SPIROM-DM6437 DEMO program
Update : 2024-05-03 Size : 6777856 Publisher : gemmy
【VHDL-FPGA-Verilog】 model DL : 0: 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
Update : 2024-05-03 Size : 7168 Publisher : momowang
【ARM-PowerPC-ColdFire-MIPS】 DDR DL : 0: S3C6410 ARM11的DDR裸机驱动编程，使用RVDS2.2配置j-linkV8调试，启动方式是nandflash-S3C6410 ARM11 DDR bare-metal programming, using the RVDS2.2 configuration j-linkV8 commissioning, start-up mode is nandflash
Update : 2024-05-03 Size : 694272 Publisher : duyb

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