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【Other】 !ddr_sdram DL : 0: ddr sram的官方文档,介绍了ddr sram的使用及其接口等各方面的消息资料.-ddr sram official documents, ddr sram introduced the use of its interface and other sources of information.
Update : 2024-05-03 Size : 452608 Publisher : wang
【File Format】 DDR_SDRAM_use_in_embedded DL : 0: 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and high-speed data acquisition, and so on the embedded system, Cache require large amounts of data. DDR (Double Data Rate, double-data rate) SDRAM due to its speed, large capacity, and their prices are cheaper, it can be a very good occasion to meet these massive data cache demand. But DDR SDRAM interface directly with today's microprocessor and DSP memory interface connected, During the need to insert controller microprocessor or DSP memory of the control.
Update : 2024-05-03 Size : 237568 Publisher : joucan
【VHDL-FPGA-Verilog】 DDR_SDRAM_Controller DL : 0: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Update : 2024-05-03 Size : 677888 Publisher : 钟方
【Linux-Unix】 tstSdram DL : 0: pnx1500 ddr test demo
Update : 2024-05-03 Size : 28672 Publisher : 曾宏
【Other】 xapp858[1] DL : 0: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input/Solution Series (ISERDES) and serial output/Solution Series (O Legacy) function.
Update : 2024-05-03 Size : 296960 Publisher : mingming
【VHDL-FPGA-Verilog】 very-good-ok-ref-ddr-sdram-verilog DL : 0: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Update : 2024-05-03 Size : 894976 Publisher : 姚明
【OS Develop】 jsjktbg1_mydown0315 DL : 0: xilinx ddr controler
Update : 2024-05-03 Size : 11264 Publisher : lanse
【Other】 leon3-altera-ep2s60-ddr DL : 0: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.-The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
Update : 2024-05-03 Size : 103424 Publisher : 岳昆
【VHDL-FPGA-Verilog】 DDRSDRAM DL : 0: DDR sdram 包含的完整的源码,仿真的相关文件-DDR sdram contains complete source code, simulation of the relevant documents
Update : 2024-05-03 Size : 1021952 Publisher : 飞翔
【VHDL-FPGA-Verilog】 ddr_ctrl DL : 0: verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
Update : 2024-05-03 Size : 27648 Publisher : 王郁
【MPI】 ddr_sdr_V1_1 DL : 0: ddr verilog代码,实现DDR内存控制，是一个高效率的程序-ddr verilog code, realize DDR memory control, is a highly efficient procedure
Update : 2024-05-03 Size : 38912 Publisher :
【Program doc】 DDR_MMC_JEDEC DL : 0: 关于DDR，DDR2,DDR3和MMC的标准规范。-On the DDR, DDR2, DDR3 and the MMC standards.
Update : 2024-05-03 Size : 13941760 Publisher : 崔海群
【Software Engineering】 v4_ddr_sdram_controller DL : 0: 利用v4fpga实现sdram ddr控制器设计，很详细的，很实用的资料-V4fpga the realization of the use of sdram ddr controller design, very detailed, very useful information
Update : 2024-05-03 Size : 417792 Publisher : hesonwhb
【Other】 JESD79E DL : 0: jesd 组织的ＤＤＲ　ＳＤＲＡＭ规范，希望对你有所帮助-DDR SDRAM Organization jesd norms, and they hope to help you
Update : 2024-05-03 Size : 939008 Publisher : feng
【Embeded-SCM Develop】 DDRinterface DL : 0: 《ALTERA FPGA/CPLD高级篇》高速DDR存储器数据接口设计实例- ALTERA FPGA/CPLD High chapter high-speed DDR memory data interface design example
Update : 2024-05-03 Size : 24576 Publisher : shicheng342
【VHDL-FPGA-Verilog】 DDRSDRAM DL : 0: 基于FPGA 实现DDR SDRAM的控制器-FPGA-based realization of DDR SDRAM controller
Update : 2024-05-03 Size : 474112 Publisher : 张宁
【VHDL-FPGA-Verilog】 DDR2_module_VHDL_test(Rev0.1) DL : 0: ddr 2 接口读写测试模块 ddr 2 接口读写测试模块 -ddr 2 interface test module ddr 2 read and write interface to read and write test module
Update : 2024-05-03 Size : 125952 Publisher : 骑士
【Software Engineering】 DDR_SDRAM_controller_verilog DL : 0: DDR SRAM控制器的verilog完整设计文档（包含有完整的verilog源代码），-DDR SRAM controller complete Verilog design documents (including a complete Verilog source code),
Update : 2024-05-03 Size : 475136 Publisher : lipengfei
【Other】 ALLEGROconstrantdesign_DDR DL : 0: ALLEGRO 约束规则设置步骤（以DDR 为例）,同样为pdf格式方便大家下载使用-ALLEGRO bound by the rules set up steps (to DDR as an example), the same for everyone to download pdf format to facilitate the use of
Update : 2024-05-03 Size : 218112 Publisher : zhang
【VHDL-FPGA-Verilog】 t26a_ibis DL : 0: ddr sdram 的控制代码，采用VHDL语言书写-ddr sdram control code, the use of VHDL language
Update : 2024-05-03 Size : 281600 Publisher : zxb

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