Introduction - If you have any usage issues, please Google them yourself
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
Packet : 81404618leon3-altera-ep2s60-ddr.rar filelist
leon3-altera-ep2s60-ddr
leon3-altera-ep2s60-ddr\.config
leon3-altera-ep2s60-ddr\ahbrom.vhd
leon3-altera-ep2s60-ddr\config.help
leon3-altera-ep2s60-ddr\config.in
leon3-altera-ep2s60-ddr\config.vhd
leon3-altera-ep2s60-ddr\config.vhd.h
leon3-altera-ep2s60-ddr\config.vhd.in
leon3-altera-ep2s60-ddr\config_test.h
leon3-altera-ep2s60-ddr\defconfig
leon3-altera-ep2s60-ddr\indata
leon3-altera-ep2s60-ddr\lconfig.tk
leon3-altera-ep2s60-ddr\leon3mp.vhd
leon3-altera-ep2s60-ddr\linkprom
leon3-altera-ep2s60-ddr\Makefile
leon3-altera-ep2s60-ddr\output_file.cof
leon3-altera-ep2s60-ddr\prom.h
leon3-altera-ep2s60-ddr\prom.srec
leon3-altera-ep2s60-ddr\README.txt
leon3-altera-ep2s60-ddr\sdram.srec
leon3-altera-ep2s60-ddr\smc_mctrl.vhd
leon3-altera-ep2s60-ddr\sram.srec
leon3-altera-ep2s60-ddr\systest.c
leon3-altera-ep2s60-ddr\testbench.vhd
leon3-altera-ep2s60-ddr\tkconfig.h
leon3-altera-ep2s60-ddr\wave.do