Search - bcd

Search - bcd - List

【SCM】 4_in_1_converter DL : 0: this program can convert binary --> gray binary --> BCD BCD --> XS3 Gray --> binary... inputs will be of 4 bits for each converter.. If you have any doubt,then mail me at prem_bombay@yahoo.co.in -this program can convert binary--> gray binary--> BCD BCD--> XS3 Gray--> binary... inputs will be of 4 bits for each converter.. If you have any doubt,then mail me at prem_bombay@yahoo.co.in
Update : 2024-05-08 Size : 1024 Publisher : Sumit
【assembly language】 binarytobcd DL : 0: binary to bcd which converts 8bit binary input to bcd -binary to bcd which converts 8bit binary input to bcd
Update : 2024-05-08 Size : 3072 Publisher : suri
【VHDL-FPGA-Verilog】 Seven-Segment-Decoder DL : 0: 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code
Update : 2024-05-08 Size : 1024 Publisher : 吴金通
【VHDL-FPGA-Verilog】 bcd_updown_counter2 DL : 0: It is a simple 4-digit bcd up down counter written in verilog
Update : 2024-05-08 Size : 1024 Publisher : jason
【VHDL-FPGA-Verilog】 bcd_adder DL : 0: verilog code for bcd adder
Update : 2024-05-08 Size : 10240 Publisher : sandeep
【SCM】 6-BCD DL : 0: 这是一个关于BCD码与二进制转换的程序，希望对大家有所帮助-BCD
Update : 2024-05-08 Size : 1024 Publisher : 刘鹏辉
【VHDL-FPGA-Verilog】 xq_Test7 DL : 0: VHDL语言编写一个BCD计数器并在七段显示数码管上显示的程序,实现了动态扫描，而且很好用-VHDL language a BCD counter and in the seven-segment display digital tube display process to achieve a dynamic scanning, and it just works
Update : 2024-05-08 Size : 144384 Publisher : 夏强
【assembly language】 bcd DL : 0: 3位BCD码转换成5位BCD码子程序-3 BCD code BCD converted into five distinctly different procedures
Update : 2024-05-08 Size : 1024 Publisher : yugioh
【assembly language】 bcd DL : 0: 汇编语言bcd乘法源代码代码正确可以直接运行-Assembly language source code for bcd multiplication can be directly run correctly
Update : 2024-05-08 Size : 1024 Publisher : 邓金桃
【assembly language】 16jinzhizhuanh DL : 0: 将给定的一个十六进制数，转换成十进制（BCD）码-Given in a hexadecimal number into decimal (BCD) code
Update : 2024-05-08 Size : 18432 Publisher : 段
【SCM】 HEXtoBCD DL : 0: 在目前所发表的十六进制转化成BCD码的处法中，一般都采用移位相加的方法，其计算过程都比较费时，不适宜很多场合，且很多不适宜C语言调用。而在C语言中，有些初学者用求余的方法来做这种运算，造成程序十分臃肿。下面这段程序仿照竖式除法来进行运算，速度超快。-Published in the current hex code into a BCD at law, in general, have adopted the method of shifting the sum of its calculation is relatively time-consuming and not suitable for many occasions and many of them not suitable for C language calls. In the C language, some beginners seeking more than the method used to do this operation, resulting in a very cumbersome process. This procedure along the lines of the following vertical division to carry out operations, super-fast.
Update : 2024-05-08 Size : 1024 Publisher : 高先生
【Other】 seven_seg_decoder DL : 0: ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no. -ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no.
Update : 2024-05-08 Size : 1024 Publisher : hassan
【File Format】 bitbcdadder DL : 0: bcd adder implemented in three models of vhdl
Update : 2024-05-08 Size : 59392 Publisher : sathishkumar
【VHDL-FPGA-Verilog】 BCD DL : 0: BCD\七段显示译码器数码管段显示发光二级管是共阴连结，所以显示高电平有效，即哪一段的驱动信号为高电平，则对应段发亮-BCD \ seven-segment display decoder digital tube sections show light-emitting diode is a link to a total of yin, it showed high and effective, that is what section of the drive signal is high, then the corresponding segment bright
Update : 2024-05-08 Size : 17408 Publisher : bryan
【VHDL-FPGA-Verilog】 BCD8 DL : 0: BCD码十进制8位加法器，采用超前进位的方法-8-bit decimal BCD adder yards, using look-ahead approach
Update : 2024-05-08 Size : 1024 Publisher : 刘骁明
【VHDL-FPGA-Verilog】 bcdseg7 DL : 0: bcd码的七段数码管显示vhdl程序 bcd码的七段数码管显示vhdl程序-bcd-yard seven-segment LED display vhdl program bcd-yard seven-segment LED display vhdl program
Update : 2024-05-08 Size : 253952 Publisher : deyi
【VHDL-FPGA-Verilog】 digital-frequency DL : 0: 数字频率计采用Verilog语言编写，分为8个模块，分别是计数器，门控，分频，寄存器，多路选择，动态位选择，BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
Update : 2024-05-08 Size : 1265664 Publisher : multidecoder
【SCM】 bcd DL : 0: 在单片机开发环境中一般会用到二进制转bcd的功能。-binary to bcd，when you use binary you can make it bcd.
Update : 2024-05-08 Size : 3072 Publisher : 朱维新
【SCM】 Bintograyconverter DL : 0: Bin to gray converter Input (DATA_IN) width : 4 Enable (EN) active : high Bin to Bcd converter Input (data_in) width : 4 Output (data_out) width : 8 Enable (EN) active : high -Bin to gray converter -- Input (DATA_IN) width : 4 -- Enable (EN) active : high Bin to Bcd converter Input (data_in) width : 4 Output (data_out) width : 8 Enable (EN) active : high
Update : 2024-05-08 Size : 1024 Publisher : haodiangei
【Software Engineering】 bai2 DL : 0: excercises verilog add two bcd numbers
Update : 2024-05-08 Size : 2287616 Publisher : atula136

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