Search - bcd

Search - bcd - List

【SCM】 pic DL : 0: pic子程序集，加减法，BCD码转换，键盘子程序-pic
Update : 2024-05-09 Size : 96256 Publisher : 绽放
【VHDL-FPGA-Verilog】 verilog_program DL : 0: 各种初学Verilog者需要练习的实例代码集锦，包含加法器，BCD计数器，2分频，交通灯等等！-Beginners need to practice a variety of examples of Verilog code highlights, including the adder, BCD counters, 2 frequency, traffic lights and more!
Update : 2024-05-09 Size : 32768 Publisher : lyh
【VHDL-FPGA-Verilog】 bcd_to_binary DL : 0: bcd to binary verilog
Update : 2024-05-09 Size : 4096 Publisher : hyuma
【Other】 BCD DL : 0: 模为 60 的 BCD码加法计数器，采用verilog语言编写。-BCD code module for the addition of 60 counters, using verilog language.
Update : 2024-05-09 Size : 1024 Publisher : kevin
【assembly language】 16-BCD DL : 0: 汇编语言实验设计关于16进制数转换为BCD码形式-Assembly language, the number of experimental design on the 16 hexadecimal form converted to BCD code
Update : 2024-05-09 Size : 1024 Publisher : TTT
【VHDL-FPGA-Verilog】 B_to_D DL : 0: 二进制转BCD码程序，可作为7段数码管显示的编解码程序，VHDL编写的FPGA工程。-BCD binary code change process, as 7 digital display codec process, VHDL FPGA project prepared.
Update : 2024-05-09 Size : 1009664 Publisher : 程光
【VHDL-FPGA-Verilog】 vhdlcoder DL : 0: 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可控脉冲发生器pluse 十一、正负脉宽数控调制信号发生器pluse width 十二、序列检测器string 十三、出租车计费器spend 十四、数字秒表selclk 十五、抢答器 first -This folder contains 16 examples of VHDL programming, only for readers to learn programming reference. 1, 4 Preset 75MHz-BCD code (plus/minus) count display (ADD-SUB). Second, light cycle display (LED-CIRCLE) 3, seven voting machines vote7 4, Gray code converter graytobin 5, a BCD code adder bcdadder six, four full adder adder4 seven or eight English letter display circuit alpher , 74LS160 counter 74ls160 9, variable-step addition and subtraction counters multicount 10, controllable pulse generator pluse 11, positive and negative pulse width modulation signal generator pluse width of NC 12, sequence detector string 13, a taxi billing spend 14 devices, digital stopwatch selclk 15, Responder first
Update : 2024-05-09 Size : 59392 Publisher : 李磊
【assembly language】 bcd DL : 0: 能够实现2个bcd码相乘，并未把结果存到已知的存储单元中-Bcd code to achieve two multiply, did not save the results to the known storage unit
Update : 2024-05-09 Size : 4096 Publisher : ljn
【VHDL-FPGA-Verilog】 bin2bcd DL : 0: 用来将二进制的信号转化成BCD码形式的信号，用来在数码管上显示相应的数字。-To the binary signal into BCD code in the form of signals, used in the digital display the corresponding number.
Update : 2024-05-09 Size : 252928 Publisher : da
【VHDL-FPGA-Verilog】 part2 DL : 0: Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2− 0. Derive a control signal, from the 50-MHz clock signal provided on the DE2 board, to increment the contents of the counter at one-second intervals. Use the pushbutton switch KEY0 to reset the counter to 0.
Update : 2024-05-09 Size : 552960 Publisher : echo
【VHDL-FPGA-Verilog】 2BCD DL : 0: 二进制转BCD码 verilog hdl Quartus II 9.0sp2 编译通过所有的文件-Binary to BCD code verilog hdl Quartus II 9.0sp2 compile all the documents
Update : 2024-05-09 Size : 286720 Publisher : 王冠
【VHDL-FPGA-Verilog】 Counter DL : 0: 计数器 QuartusⅡ 10进制计数器 CLKIN为时钟输入端，CLR为清零端，Y[3..0]为四位二进制输出（BCD 码形式），CLKOUT为10进制计数器进位输出端 -Counter
Update : 2024-05-09 Size : 29696 Publisher : duopk
【VHDL-FPGA-Verilog】 bcd_to_7segmentos DL : 0: bcd to 7 segments display tested on xboard xilinx, all code developed on vhdl
Update : 2024-05-09 Size : 602112 Publisher : carlos
【VHDL-FPGA-Verilog】 999jisq DL : 0: 一个能从0~999计数的 bcd码数码管电路-A count from 0 to 999 digital control circuit bcd code
Update : 2024-05-09 Size : 86016 Publisher : 黄国猛
【Windows Develop】 bcd DL : 0: WINDOWS 7 和 XP启动BCD编辑工具!-WINDOWS 7 and XP start BCD editor!
Update : 2024-05-09 Size : 155648 Publisher : th1nk
【VHDL-FPGA-Verilog】 vhdl DL : 0: 用VHDL语言实现的二进制到BCD码和格雷码的转换，程序通读性比较好。-VHDL language with the binary code and Gray code to BCD conversion, the program read through is better.
Update : 2024-05-09 Size : 1024 Publisher : 周波
【assembly language】 bcd DL : 0: 三字节转BCD双字节十六进制整数转换成双字节ＢＣＤ码整数.txt-Three-byte transfer byte BCD integer into a double-byte hexadecimal integer BCD code. Txt
Update : 2024-05-09 Size : 1024 Publisher : zxs
【VHDL-FPGA-Verilog】 BCD DL : 0: ROM vhdl for binary to BCD
Update : 2024-05-09 Size : 1024 Publisher : K1000
【SCM】 02-BCD-Conv DL : 0: 关于单片机bcd的应用程序，希望对大家有帮助！-Bcd on the MCU application, we want to help!
Update : 2024-05-09 Size : 18432 Publisher : 杨镇宁
【SCM】 07-BCD-NEG DL : 0: 关于单片机bcd neg的应用程序，希望对大家有帮助！-SCM bcd neg on application, we want to help!
Update : 2024-05-09 Size : 25600 Publisher : 杨镇宁

« 1 2 ... 5 6 7 8 9 1011 12 13 14 15 ... 50 »