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【SCM】 08-BCD-Add DL : 0: 关于单片机bcd ADD的应用程序，希望对大家有帮助！-SCM bcd ADD on the application, we want to help!
Update : 2024-05-20 Size : 5120 Publisher : 杨镇宁
【SCM】 09-BCD-Sub DL : 0: 关于单片机bcd SUB的应用程序，希望对大家有帮助！-SCM bcd SUB on the application, we want to help!
Update : 2024-05-20 Size : 27648 Publisher : 杨镇宁
【SCM】 10-BCD-Shift DL : 0: 关于单片机bcd SHIFT的应用程序，希望对大家有帮助！-SCM bcd SHIFT on the application, we want to help!
Update : 2024-05-20 Size : 18432 Publisher : 杨镇宁
【VHDL-FPGA-Verilog】 BCD DL : 0: 编译完成并分配了管脚后，利用EDA6000启动电路，利用两个四位拨码开关实现两个BCD码的输入，通过数码管显示的结果表明电路设计结果符合预期，能正确的完成BCD码的加法。-Compilation and distribution of the pin, the use of EDA6000 start circuit, using two four DIP switches to achieve two BCD code input, through the digital display of the results showed that the circuit design results in line with expectations, correctly complete the BCD code addition.
Update : 2024-05-20 Size : 161792 Publisher : 吴琦轩
【VHDL-FPGA-Verilog】 bin2bcd7seg DL : 0: 用vhdl语言编译一个码制转换四位二进制->BCD码，然后将BCD码->七段显示器码。（1）当输入为0~9的数时，其十位数为0，个位数=输入。当输入为10~15的数时，其十位数为1，个位数=输入-10。（2）然后将十位和个位的BCD码转换为七段显示码 -Vhdl language used to compile a binary code system conversion of four-> BCD code, then BCD code-> seven-segment display code. (1) When the input is a number from 0 to 9, its ten digits 0 digits = input. When the input is 10 to 15 the number, the tens digit is 1, digits = input-10. (2) and then ten and a bit BCD code is converted to seven segment display code
Update : 2024-05-20 Size : 326656 Publisher : 宋子皓
【VHDL-FPGA-Verilog】 bcd-alu DL : 0: 一位十进制bcd加减法运算器,可对两个一位整数进行加减法运算.-Bcd a decimal addition and subtraction operations, which can be both an integer addition and subtraction operations.
Update : 2024-05-20 Size : 462848 Publisher : k.lin
【VHDL-FPGA-Verilog】 VHDL-3BCD DL : 0: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data.
Update : 2024-05-20 Size : 56320 Publisher : will li
【Embeded-SCM Develop】 24-bit-binary-to-4-byte-BCD DL : 0: 24-bit binary to 4-byte BCD for 8051 microcontroller
Update : 2024-05-20 Size : 3072 Publisher : microorganisme
【Embeded-SCM Develop】 NO.10-BCD-decoding-digital DL : 0: 《单片机C语言程序设计实训100例——基于8051+Proteus仿真》案例压缩包第 02 篇第 02 篇硬件应用 10 BCD译码数码管显示数字-" Microcontroller C Programming Language Training 100 cases- based on 8051+ Proteus simulation," Case No. 02 cabinet hardware section 02 application 10 BCD decoding digital display digital
Update : 2024-05-20 Size : 30720 Publisher : 王小明
【Software Engineering】 bcd-adder DL : 0: its bcd progrrame in mentor graphics
Update : 2024-05-20 Size : 3072 Publisher : sreenivasulu
【VHDL-FPGA-Verilog】 BCD_add DL : 0: BCD全加器，用QuartuesII 开发的源码，包括工程文件，下载就能用的，在DE2-70上直接使用。-BCD full adder, with QuartuesII source development, including the project file, download will be able to use in directly on the DE2-70.
Update : 2024-05-20 Size : 313344 Publisher : ricky
【Software Engineering】 A-New-Reversible-Design-of-BCD-Adder DL : 0: Designing a BCD adder
Update : 2024-05-20 Size : 104448 Publisher : Anand
【VHDL-FPGA-Verilog】 BCD2LED DL : 0: bcd to led decoder file-bcd to led decoder file..
Update : 2024-05-20 Size : 1024 Publisher : praveenkumardr
【Embeded-SCM Develop】 bcd DL : 0: 星研版单片机实验 BCD码双字节乘法小键盘输入-Star research version of the chip experiment double-byte BCD code multiplication
Update : 2024-05-20 Size : 1024 Publisher : 曾牧
【SCM】 BCD DL : 0: 51单片机实现，用汇编实现BCD码的十进制加法，低位不带进位加法，高位带进位加法-51 assembly to achieve BCD coded decimal addition
Update : 2024-05-20 Size : 9216 Publisher : liwenjin
【VHDL-FPGA-Verilog】 A-Novel-Reversible-BCD-Adder-For-Nanotechnology-B DL : 0: A Novel Reversible BCD Adder For Nanotechnology Based System
Update : 2024-05-20 Size : 190464 Publisher : Christoffer
【VHDL-FPGA-Verilog】 Design-and-Optimization-of-Reversible-BCD-Adder-S DL : 0: Design and Optimization of Reversible BCD Adder-Subtractor Circuit
Update : 2024-05-20 Size : 78848 Publisher : Christoffer
【VHDL-FPGA-Verilog】 Design-of-Optimized-Reversible-BCD-Adder-Subtract DL : 0: Design of Optimized Reversible BCD Adder-Subtractor 229
Update : 2024-05-20 Size : 790528 Publisher : Christoffer
【VHDL-FPGA-Verilog】 Optimized-reversible-BCD-adder-using-new DL : 0: Optimized reversible BCD adder using new
Update : 2024-05-20 Size : 265216 Publisher : Christoffer
【assembly language】 Convert-binary-to-BCD DL : 0: 计算机中的数值有各种表达方式，这是计算机的基础。掌握各种数制之间的转换是一种基本功。二进制到BCD转换-There are a variety of computer numerical expression, which is the basis for the computer. Of various kinds of number system conversion between a basic skills. Convert binary to BCD
Update : 2024-05-20 Size : 5120 Publisher : 范志豪

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