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【VHDL-FPGA-Verilog】 MinWinsockSpi DL : 0: verilog ADPLL file with testbench
Update : 2024-05-02 Size : 197632 Publisher : xgh
【VHDL-FPGA-Verilog】 SPI_FireWall DL : 0: verilog spi file with testbench
Update : 2024-05-02 Size : 2934784 Publisher : xgh
【Windows CE】 wince+spi DL : 0: verilog vcspi file with testbench
Update : 2024-05-02 Size : 1944576 Publisher : xgh
【Com Port】 UART DL : 0: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Update : 2024-05-02 Size : 9216 Publisher : 李佳
【VHDL-FPGA-Verilog】 RAMtestbench DL : 0: 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
Update : 2024-05-02 Size : 1024 Publisher : 赵国栋
【Other】 Verilogtestbench DL : 0: Writing Testbenches classic book in verilog testbench-Writing Testbenchesclassic book in verilog testbench
Update : 2024-05-02 Size : 57344 Publisher : dan
【ARM-PowerPC-ColdFire-MIPS】 risc DL : 0: 嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
Update : 2024-05-02 Size : 129024 Publisher : 李林
【VHDL-FPGA-Verilog】 adder4 DL : 0: 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
Update : 2024-05-02 Size : 1024 Publisher : olive
【VHDL-FPGA-Verilog】 custom_cordic DL : 0: verilog编程开发的cordic例程，计算SIN,COS功能与计算幅值角度功能可设定，运算宽度可设定，并有完善的TESTBENCH。-Verilog programming developed CORDIC routines to calculate SIN, COS function and calculating the amplitude of the perspective of function can be set, computing the width can be set, and perfect TESTBENCH.
Update : 2024-05-02 Size : 119808 Publisher : yangyu
【SCM】 8051_IP_Verilog DL : 0: 8051单片机源码verilog版本包括rtl， testbench， synthesis -Verilog source code version of 8051, including rtl, testbench, synthesis
Update : 2024-05-02 Size : 508928 Publisher : carol
【VHDL-FPGA-Verilog】 Am29lv160d DL : 0: 在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d），包括VHDL代码文件和verilog代码文件和testbench，并且有相应的pdf说明文档。-In the logic system used in FLASH simulation model (AMD s Am29lv160d), including VHDL and Verilog source code files of documents and testbench, and the corresponding pdf documentation.
Update : 2024-05-02 Size : 216064 Publisher : 天策
【source in ebook】 XiaYuWen_8_RISC_CPU DL : 0: 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶化，综合时很可能会setup vio的，所以觉得直接用clk的上升沿来触发各个module比较好-XIA Yu-Wen 8 RISC_CPU complete code+ TESTBENCH (has debug) modelsim project documents, including the book by the three test procedures and related data, the absolute available ~ all signals were found in compliance with the original name. Not found in the forums Testbench, and there is only one mcu code, but many and the book is not the same as he changed a lot of support under the U.S. ~````` ah ~ `I think the book is still some uncertainty unsatisfactory places, such as clk_gen.v in clk2, clk4 is of no use, assign clk1 = ~ clk reuse CLK1 of negedge clk1 to trigger module is not all good, cause the deterioration of timing, synthesis is likely to setup vio, therefore, feel that the direct use of the rising edge of clk to trigger each module is better
Update : 2024-05-02 Size : 86016 Publisher : 刘志伟
【Other】 testbench DL : 0: ddr sdram controller datd module source code
Update : 2024-05-02 Size : 3072 Publisher : KrishnaKishore
【VHDL-FPGA-Verilog】 spi2-testbench DL : 0: test bench for spi communication
Update : 2024-05-02 Size : 1024 Publisher : Onur
【Windows Develop】 testbenchcpu8080 DL : 0: this is code testbench cpu -this is code testbench cpu 8080
Update : 2024-05-02 Size : 6144 Publisher : minh
【VHDL-FPGA-Verilog】 vrt DL : 0: Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis
Update : 2024-05-02 Size : 138240 Publisher : 宁宁
【VHDL-FPGA-Verilog】 hssdrc_latest.tar DL : 0: HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License
Update : 2024-05-02 Size : 424960 Publisher : Arun
【Embeded-SCM Develop】 pcie_vera_tb_latest.tar DL : 0: FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs -FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs
Update : 2024-05-02 Size : 169984 Publisher : Arun
【VHDL-FPGA-Verilog】 generic_testbench DL : 0: VHDL中关于generic的用法，及其testbench，可以使用Modelsim仿真查看其功能-the usage of generic,a testbench file is given, we can use it to simulate the generic s function
Update : 2024-05-02 Size : 2048 Publisher : xietianjiao
【Other】 testbench DL : 0: 有关FPGA测试平台的书写的经典资料，不过是英文的-FPGA test platform of the classic of writing data, but in English
Update : 2024-05-02 Size : 950272 Publisher : 许伟

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