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【SCM】 fifo DL : 0: 一个同步FIFO，包括testbench，-A synchronous FIFO, including the testbench,
Update : 2024-05-02 Size : 1024 Publisher : 张丰
【Other】 i2c DL : 0: I2C controller的源码，包括TESTBENCH在内，里面包含有EEPROM的behaving model，前些日子在本站下了一个EEPROM的behaving model，发现可能只是作者的初版，里面错误比较多，因此上传一个能编译拿过来就能用的环境。-I2C controller source code, including the Testbench included, which contains EEPROM
Update : 2024-05-02 Size : 16384 Publisher : 二马
【Other】 testbench DL : 0: 一个自己编写的全数字锁相环及其测试向量，比较简单但功能基本达到。-I have written an all-digital phase-locked loop and its test vectors, relatively simple to achieve but the basic function.
Update : 2024-05-02 Size : 30720 Publisher : liujl
【VHDL-FPGA-Verilog】 core_arm.tar DL : 0: vhdl的arm核包含testbench-VHDL Testbench contain the nuclear arm
Update : 2024-05-02 Size : 666624 Publisher : dc
【Software Engineering】 guiden-to-write-efficient-testbench DL : 0: 这是一个xilinx公司发布的写testbenth的入门向导，指导我们快速高效的写自己的testbenth，从而改进我们的仿真效果。 -This is a Xilinx Inc. released testbenth write entry wizard, guiding us to quickly and efficiently write their own testbenth, in order to improve our simulation effect.
Update : 2024-05-02 Size : 197632 Publisher : 罗肖
【Other】 testbench DL : 0: 32位除法器的测试程序，由随机向量产生函数产生一组随机数来验证计算书否正确-32 divider test procedures, by the random vector generated a set of functions to generate random numbers to verify whether the correct calculation of the book
Update : 2024-05-02 Size : 5120 Publisher : 李春阳
【Communication】 ddstest DL : 0: 实现dds的testbench，很有帮助-Dds to achieve the testbench, helpful
Update : 2024-05-02 Size : 1110016 Publisher : 罗伟
【VHDL-FPGA-Verilog】 counter DL : 0: VHDL计数器的TestBench，适合初学者-VHDL counter TestBench, suitable for beginners
Update : 2024-05-02 Size : 1024 Publisher : hbsun
【Software Engineering】 Verifying_the_Quality_of_Your_Testbench_with_code_ DL : 0: Testbenches have become an integral part of the design process, enabling you to verify that your HDL model is sufficiently tested before implementing your design and helping you automate the design verification process. It is essential, therefore, that you have confidence your testbench is thoroughly exercising your design. Collecting code coverage statistics during simulation helps to ensure the quality and thoroughness of your tests.-Testbenches have become an integral part of the design process, enabling you to verify thatyour HDL model is sufficiently tested before implementing your design and helping you automatethe design verification process. It is essential, therefore, that you have confidence yourtestbench is thoroughly exercising your design. Collecting code coverage statistics during simulationhelps to ensure the quality and thoroughness of your tests.
Update : 2024-05-02 Size : 258048 Publisher : daniel
【VHDL-FPGA-Verilog】 dac DL : 0: DAC converter design with Verilog code and testbench
Update : 2024-05-02 Size : 527360 Publisher : 田磊
【VHDL-FPGA-Verilog】 I2C_HDL DL : 0: I2C bus HDL source and testbench
Update : 2024-05-02 Size : 701440 Publisher : liuKe
【MPI】 i2c.tar DL : 0: i2c总线控制器ipcore，包含testbench-i2c bus controller ipcore, contains Testbench
Update : 2024-05-02 Size : 643072 Publisher : 吴飞
【VHDL-FPGA-Verilog】 WritingTestbenches DL : 0: 编写testbench的超好教程，网上这种资料比较少。(Kluwer) Writing Testbenches--Functional Verification of HDL Models.pdf-Testbench prepared super good tutorials, on-line this information is relatively small. (Kluwer) Writing Testbenches Functional Verification of HDL Models.pdf
Update : 2024-05-02 Size : 4112384 Publisher : 文成
【Crack Hack】 test_bench_top DL : 0: 用于AES加密的testbench。产生激励-AES encryption for testbench. Incentive
Update : 2024-05-02 Size : 10240 Publisher : zsh
【VHDL-FPGA-Verilog】 tb_w DL : 0: 简单的testbench制作方法，对初学者有点帮助-Testbench simple manufacturing method, for beginners a little help
Update : 2024-05-02 Size : 1024 Publisher : yang
【Other】 ArtofWritingTestBenches DL : 0: Art of Writing TestBenches：极经典的testbench书写入门书籍，能够让初学者在短时间内掌握testbench的书写步骤，对testbench有一个初步的认识，这是一个verilog方面的，没找到verilog就选了开发环境为vhdl-Art of Writing TestBenches: very classic entry Testbench writing books, that allows beginners to master in a short time Testbench writing steps Testbench have a preliminary understanding, this is a Verilog area, could not find Verilog development environment on selected for VHDL
Update : 2024-05-02 Size : 97280 Publisher : 侯浩
【VHDL-FPGA-Verilog】 trueif DL : 0: 一个超前进位加法器（及其testbench) .v文件-A CLA (and its testbench). V file
Update : 2024-05-02 Size : 1024 Publisher : QU YIFAN
【VHDL-FPGA-Verilog】 crc16_ccitt DL : 0: crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module. -crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.
Update : 2024-05-02 Size : 3072 Publisher : 樊文杰
【VHDL-FPGA-Verilog】 textio DL : 0: vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!-vhdl testbench preparation, textio the preparation is a difficult, but also a focus, and this is my collection of articles on textio the article, at the same time with a simple note!
Update : 2024-05-02 Size : 1327104 Publisher : horse
【Books】 testbench DL : 0: IC验证，一本不可多得的好书，讲的非常全面。-IC verification, a rare book, talking about very comprehensive.
Update : 2024-05-02 Size : 702464 Publisher : zjy

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