Search - TestBench

Search - TestBench - List

【Other】 Lpfilter_20190503 DL : 0: 环路滤波器是通信信号调制解调中最重要的一个部分，环路滤波器设计的好坏将直接影响到接收机的性能指标，二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源，是现代通信中非常实用的技术，本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块，并包含了完整的testbench模块，对于初学者非常有用。(Loop filter is the most important part of communication signal modulation and demodulation. The design of loop filter will directly affect the performance index of receiver. The second-order frequency locking assisted third-order phase-locked loop filter can stably track the signal source with acceleration speed, which is a very practical technology in modern communication. In this paper, the single carrier signal generation module and channel noise are written in detail Sound module, digital orthogonal down conversion module, frequency and phase detection module, loop filter module, and contains a complete testbench module, which is very useful for beginners.)
Update : 2024-05-02 Size : 6156288 Publisher : furypie
【assembly language】 fulladder的sv文件 DL : 0: fulladder的sv文件，有testbench。
Update : 2021-04-22 Size : 927 Publisher : yangxingchen19@163.com
【3G develop】 RS纠错码的实现 DL : 0: RS纠错码的编码实现verilog语言可以运行，并包含testbench，可以进行测试适用于初学者
Update : 2021-05-07 Size : 5142 Publisher : 1228721125
【VHDL-FPGA-Verilog】 LSFR design DL : 0: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model.
Update : 2022-09-13 Size : 93658 Publisher : essaidioualid@gmail.com
【e-language】 Anti-shattering HDL DL : 0: Parametric HDL contact shatter protection module. There is a testbench
Update : 2024-01-29 Size : 2289 Publisher : Murman

« 1 2 ... 40 41 42 43 44 45»