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【Editor】 i2c_testbench DL : 0: i2c verilog rtl with testbench very good code and works perfectly with cadence ius and ncverilog
Update : 2024-05-17 Size : 11264 Publisher : akash man
【VHDL-FPGA-Verilog】 16_sd_test DL : 0: sd卡的测试工程 sd卡的测试工程 sd卡的测试工程-sd card testbench
Update : 2024-05-17 Size : 2169856 Publisher : 马森
【Other】 Functional-Verification DL : 0: 该书籍是testbench教程里面的经典之作，对于初学验证的同学来说，强烈推荐！- U8BE5 u4E66 u7C4D u662Ftestbench u6559 u7A0B u91CC u9762 u7684 u7ECF u5178 u4E4B u4F5C uFF0C u5BF9 u4E8E u521D u5B66 u9A8C u8BC1 u7684 u540C u5B66 u6765 u8BF4 uFF0C u5F3A u70C8 u63A8 u8350 uFF01
Update : 2024-05-17 Size : 2137088 Publisher : 陈卓
【source in ebook】 fpga DL : 0: 有关FPGA的好多资料的综合汇总，包括夏宇闻-Verilog经典教程，Verilog-testbench的写法，Altera+FPGA／CPLD设计高级篇，Altera+FPGA／CPLD设计基础篇等好几本书，超值-A comprehensive summary of a lot of information about FPGA, including Xia Wen-Verilog classic tutorial, Verilog-testbench writing, senior Altera+FPGA/CPLD/CPLD design, Altera+FPGA design based on articles such as several book value
Update : 2024-05-17 Size : 48264192 Publisher : libao
【Software Engineering】 2D-DCTVERILOG DL : 0: 2D DCT VERILOG CODE WITH TESTBENCH WHICH HAVING 1D DCT TRANSPOSE MATRIX
Update : 2024-05-17 Size : 31744 Publisher : peddinti.rajasekhar
【VHDL-FPGA-Verilog】 firfilterPfpga DL : 0: FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench
Update : 2024-05-17 Size : 9401344 Publisher : dfdqzp
【VHDL-FPGA-Verilog】 DDS DL : 0: 利用ISE中的ip核产生正弦和余弦波形，包含有test测试文件-ISE ip core cosine sine testbench
Update : 2024-05-17 Size : 5760000 Publisher : dfdqzp
【Other】 Parallel_LDPC_Sim DL : 0: 并行LDPC的测试工程，包括编解码，和双码字之间的能量泄露比例；-testbench for parallel ldpc codec
Update : 2024-05-17 Size : 1024 Publisher : 张健
【Linux-Unix】 code_test DL : 0: uvm testbench 例子，可以在questa软件里运行，运用shell脚本，在cygwin环境中执行，非常方便-Uvm testbench example, you can run in questa software, the use of shell script, in cygwin environment, very convenient
Update : 2024-05-17 Size : 1205248 Publisher : 徐伟升
【Other】 tiuning DL : 0: The true extent of the value of the intermediary measure, measure the true extent of the agency based on the value of image segmentation Multivariate least squares fitting method of nonlinear equations, Genetic algorithm based reactive power optimization.
Update : 2024-05-17 Size : 4096 Publisher : seisoufuibao
【Graph program】 tunjiu DL : 0: IDW inverse distance weighting method, The signal spectral analysis and filtering, This program has exceeded the performance of other algorithms.
Update : 2024-05-17 Size : 4096 Publisher : bunbaoquining
【VHDL-FPGA-Verilog】 I2C_slaver_verison3.0 DL : 0: I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
Update : 2024-05-17 Size : 2095104 Publisher : wenxulyu
【VHDL-FPGA-Verilog】 sdram DL : 0: sdram的控制程序，以及相关的testbench(sdram control module)
Update : 2024-05-17 Size : 128000 Publisher : 大地2020
【VHDL-FPGA-Verilog】 seq DL : 0: 实现序列检测功能，新手编程，已经在modelsim里检验过了功能完整，内附模块化testbench(Sequence detection function, novice programming)
Update : 2024-05-17 Size : 2048 Publisher : 橙鸽
【VHDL-FPGA-Verilog】 eetop.cn_UVM DL : 0: UVM 的入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，(UVM entry example, a complete example of running through. These include the DUT code, the Testbench code,)
Update : 2024-05-17 Size : 3037184 Publisher : 西麦
【VHDL-FPGA-Verilog】 New folder DL : 0: clock div testbench design and frquency division
Update : 2024-05-17 Size : 3072 Publisher : Bharadwaj
【VHDL-FPGA-Verilog】 SEQ_DETECTOR DL : 0: 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data), decrement mode (detecting four consistency decrement data) and steadiness mode (detecting four consistency same data). The whole design adopts synchronous clock, asynchronous reset, and uses Mealy state machine. The whole file concludes the simulation environment and testbench.)
Update : 2024-05-17 Size : 1855488 Publisher : LLawliet
【Other】 System_Verilog_for_Verification_3nd_Edition DL : 0: SystemVerilog for Verification A Guide to Learning the Testbench Language Features The 3nd Edition
Update : 2024-05-17 Size : 8180736 Publisher : ajianer
【VHDL-FPGA-Verilog】 apb_uart DL : 0: 带apb接口的uart,带testbench，测试过，可以使用(The uart module with apb interface)
Update : 2024-05-17 Size : 3072 Publisher : songchao
【VHDL-FPGA-Verilog】 multiplier_TB DL : 0: multiplier testbench
Update : 2024-05-17 Size : 1024 Publisher : happywater12

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