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【Embeded-SCM Develop】 148个verilog hdl小程序（有很多testbench）—— DL : 5: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Update : 2008-10-13 Size : 56068 Publisher : 地方
【Other resource】 testbench DL : 0: 编写testbench的非常号的参考资料哦。
Update : 2008-10-13 Size : 244936 Publisher : 文成
【Other resource】 Testbench DL : 0: 单顶层结构化Testbench设计实例，适合硬件开发人员作为参考
Update : 2008-10-13 Size : 154933 Publisher : xyq
【Other resource】 testbench DL : 0: 一片英语文章，详细描述了testbench的编写，尤其是assert和textio的用法，老外的文章就是不一样，看了之后让人茅塞顿开
Update : 2008-10-13 Size : 2094835 Publisher : horse
【Documents】 how to write testbench DL : 0: 很好的，适合初学者Writing Efficient Testbenches
Update : 2009-03-13 Size : 196792 Publisher : applehot@126.com
【Documents】逻辑验证与Testbench 编写 DL : 0: 逻辑验证与Testbench 编写
Update : 2009-04-10 Size : 285391 Publisher : bingxinhuier
【VHDL-FPGA-Verilog】 testbench模版 DL : 0: testbench测试模版
Update : 2010-11-04 Size : 664 Publisher : lmyapple
【Program doc】 testbench设计精华 DL : 0: 介绍FPGA中testbench设计技巧
Update : 2011-01-07 Size : 56320 Publisher : xiazgjay@163.com
【VHDL-FPGA-Verilog】比较器的测试矢量 DL : 0: 一个很好的testbench的例子。
Update : 2011-10-28 Size : 3934 Publisher : daxuerushui
【Crack Hack】 rom_des DL : 0: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Update : 2024-05-02 Size : 30720 Publisher :
【VHDL-FPGA-Verilog】 flash接口控制_verilog DL : 0: flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
Update : 2024-05-02 Size : 870400 Publisher : 李楠
【VHDL-FPGA-Verilog】 vhdl实现alu的源代码 DL : 0: VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!
Update : 2024-05-02 Size : 1024 Publisher : 飞扬
【Crack Hack】 MD5(verilog) DL : 0: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
Update : 2024-05-02 Size : 4096 Publisher : 张雷
【VHDL-FPGA-Verilog】 H16550_2[1].0V DL : 0: 专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550 ，包含完整的使用说明手册、testbench、可综合，如果被网站认可，将继续上传其余的几个更好的core。-specialized processor and peripheral interfaces famous ipcore CAST product manufacturers UART H16 550, including full use manual testbench can be integrated, if the site is approved, the rest will continue to upload a few better core.
Update : 2024-05-02 Size : 386048 Publisher : 宋云成
【VHDL-FPGA-Verilog】 generic_fifo DL : 0: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Update : 2024-05-02 Size : 20480 Publisher : daiowen
【VHDL-FPGA-Verilog】 wave_gen DL : 0: 波形发生器，带TESTBENCH，多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
Update : 2024-05-02 Size : 1024 Publisher : 罗兰
【Other】 Art_of_writing_testbenches DL : 0: Art_of_writing_testbenches,学习写testbench的经典书籍-Art_of_writing_testbenches. Learning to write the classic books testbench
Update : 2024-05-02 Size : 78848 Publisher : william
【VHDL-FPGA-Verilog】 mdct.tar DL : 0: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Update : 2024-05-02 Size : 1767424 Publisher : 陈朋
【VHDL-FPGA-Verilog】 ADPLL DL : 2: verilog ADPLL file with testbench.v
Update : 2024-05-02 Size : 25600 Publisher :
【VHDL-FPGA-Verilog】 Modsim-AND-testbench DL : 0: 关于fpga中，测试平台testbench的技巧，及仿真软件MOSIDISIM-About fpga skills test platform testbench, and simulation software MOSIDISIM
Update : 2024-05-02 Size : 6334464 Publisher : kehuan

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